Good questions.
1) Does REF_CLK must be routed without vias.
Whenever you see something like "must be routed without vias" without a good explanation, chances are that someone does not fully understand what is going on and just think that is a good idea.
One of several things may be the issue:
- Different trace impedance on different layers, which will cause reflections whenever there is a via.
- Reference plane problem, because the impedance between the power planes of the design is not low enough.
Both of these are easy to avoid and is good practice - often even required if you want to pass EMI tests, build a solid design etc.
So provided you do this, you can use vias without any issues. The faster the signals, the more careful you have to design the vias. I have previously written about how to design vias for 28+ GBps signals here.
2) Does REF_CLK need termination resistor?
Best thing to do here is a quick simulation with your favorite IBIS simulator - or have someone do that for you (sorry, these tools costs money - but are worth it).
If you have very fast edge rates, chances are you need a termination resistor if the trace is electrically longer than about 1/3 of the rise/fall time. Use simulation to be sure (unfortunately you did not provide enough information about your design, or I might just have done it right away).
3) Is 4mm difference in trace length @50Mhz acceptable?
Another good question. Look at the rise/fall times of your signal. If the electrical length of the rise/fall time is significantly longer than the trace length mismatch, this will work just fine. Actually it is a good practice not to overconstrain layouts, even though it is often possible to match trace lenghts within a very narrow tolerance.
So it turns out an RMII Phy can talk to another RMII phy like this but the LAN9303 can't be connected directly to another LAN9303 as described. The problem is that timing of the DV D0 and D1 signals coming out of one LAN9303 don't meet the requirements for DV D0 and D1 going into the other. The data needs to be moved to the opposite clock edge for this approach to work.
Best Answer
MII runs at 25Mhz, so at that speed transmission line effects are usually not seen. RMII runs at 50Mhz which does need impedance matching and the DP83640 uses 50Ω matching so build your PCB traces for 50Ω if using RMII.
RGMII uses 2.5V CMOS or 1.8V HSTL at 125Mhz
You use HSTL if you have transceivers to do so, this also implies matching
2.5V CMOS will need to have a matched transmission line for whatever port it is being driven from (either microprocessor or FPGA) and the PHY