Inside_process : process(clk)
begin
if clk='1' and clk'event then
signal1 <= signalin;
signal2 <= signal1;
end if;
Out_signal <= signal1 and (not signal2);
end process Inside_process;
end rtl;
VS
Outside_process : process(clk)
begin
if clk='1' and clk'event then
signal1 <= signalin;
signal2 <= signal1;
end if;
end process Outside_process;
Out_signal <= signal1 and (not signal2);
end rtl;
I see in some codes signal assignments are made inside processes and sometimes just a bit before end rtl;
in this case rtl is architecture. Sometimes many signals are assigned outside process sometimes many. In above example I get no synthesis error and the my circuit works with both versions. So I don't understand what is the difference between them also some signals can't be assigned in the process they have to be outside and they make difference! Why can some be assigned in process why some not? Why sometimes it doesn't make difference? Also how frequently are the signals assigned outside the process, every rising clock edge? Every 5th rising clock edge? How is it decided? What is the use of assigning a signal outside the processes? If I'm going to assign a signal outside a process I usually do it before end rtl;
(the last line). I noticed it doesn't hurt doing this between 2 processes as well, so doesn't have to be just before the last line, can be in the middle as well.
If I should give an example signal assignment in process which gives an error :
d3 <= r4 when (sn(3)='1') else d2;
Error msg: parse error, unexpected WHEN, expecting SEMICOLON.
There is a semicolon actually. But when this line is taken out of the process, it works. I don't understand how, if someone can enlighten me I would be glad.
Also in VHDL shall I declare processes uppercase letters, signals lowercase letters, or everything uppercase? Is there a common usage and discipline? For example it isn't encouraged in Java for variables to start with uppercase? If there is a common usage like this for VHDL, can I get a link for that?
Best Answer
Only sequential statements are allowed inside a process statement. An architecture statement part is comprised of zero or more concurrent statements. rtl appears to be the name of architecture and a process statement is a concurrent statement.
Notice from your referenced code you are having problems with:
That the line you ask about in your question is line 54:
And that this a concurrent signal assignment and yet it is showing up in a process statement (the domain of sequential statements).
The form of this is a 'conditional signal assignment', which happens to have been added to sequential signal assignments by IEEE Std 1076-2008 (10.5.3 Conditional signal assignments, § 10 is entitled Sequential statements).
And from this we can infer that while Modelsim supports the 2008 VHDL standard, your XST doesn't (error messages of the form 'ERROR:HDLParsers:' are XST messages).
If and when Xilinx would support synthesis of conditional signal assignment statements within a process (as sequential signal assignment) is a matter of versions and/or policy. There's no particular difference in difficulty of synthesis to support it, while representing significant change in the parser.
VHDL is case insensitive except in extended identifiers and character literals.
From IEEE Std 1076-2008 15.2 Character set:
And 15.4 Identifiers:
addendum
There's an obvious difference between the two processes. The one with the concurrent signal assignment(
Outside_process
) will haveOut_signal
show change immediately upon change update for signalssignal1
andsignal2
because the concurrent signal assignment will have an equivalent process containing a sequential signal assignment statement and a sensitivity list equivalent containingsignal1
andsignal2
. (Every signal appearing on the right hand side of a signal assignment statement).The process
Inside_process
only hasclk
in the sensitivity list, meaning in simulationOut_signal
will be assigned at the nextclk'EVENT
, an apparent half clock delay because the assignments to your two shift register signals are visible in the next delta cycle.See this stackoverflow answer The VHDL Simulation Cycle as well as this one - Unexpected delays with register VHDL.
Interestingly enough both will probably synthesize identically because the sensitivity list will either be disregarded or updated (assumed to include
signal1
andsignal2
inInside_process
). Any assumptions should likely show up in warnings.Elaboration devolves a design description into block statements (maintaining hierarchy), process statements and function calls. All concurrent statements have a process statement equivalent, potentially within block statements (or nested block statements). In the case of simple signal assignment statements there is little observable difference between signal assignment inside or outside a process (except the sensitivity list which in this case is incomplete for
Inside_process
).A design specification will be elaborated before simulation and as a predicate for synthesis as well.