Your code is not quite right.
If you want to set something to a value, you need to create a register and set it accordingly, then assign the value to an output. Generally you cannot use initial statements for synthesis (check your documentation) so setting the register to a constant on a reset signal, or using a ROM block are options.
Let's say you want to flash the LEDs though, this is more exciting than just turning them on. Say we have a 16MHz clock, to slow the clock down so the LEDs flash visibly, we need to divide it down. If we pick a 24 bit count register, 16e6 / (2^24) = ~1Hz so LEDs will update once per second.
module fpga(
input clk,
output LEDG[7:0);
// output reg to set
reg rOUT[7:0]
// counter reg to slow clock down
reg rCOUNT[24:0]
// this models the synchronous logic, the block is activated on each positive edge of clk
always(@ posedge clk)
begin
// add one to rCOUNT on each clock positive edge
rCOUNT <= rCOUNT + 1;
// if rCOUNT equals 0xFFFFFF then increment rOUT by 1
if(rCOUNT == 24'hFFFFFF)
begin
rOUT <= rOUT + 1;
end
end
assign value of rOUT to LEDG so LEDs will light according to rOUTs current value
assign LEDG = rOUT;
endmodule
Note that when assigning a value to a register, you need to specify the width otherwise it will default to the default width of the system (e.g. 32 bits)
So if you create an 8 bit register rOUT and you want to set it to all 1's, then assuming your sythesis software allows assigning an intitial value you would write reg rOUT = 8'b11111111; or reg rOUT = 8'hFF;
This will all become clear as you read more.
About the Quartus pin planner, I'm not sure (as I use Xilinx/Actel FPGAs), but make sure the pin assignments are correct. YOu should be able to either change them in the pin planner or manually edit the constraints file as necessary. It will all be there in the (no doubt very lengthy) documentation.
A good book is "FPGA Prototyping by Verilog Examples" (Pong P Chu), but there are some examples out there you can follow - fpga4fun is a good site with many example projects. Spend some time reading and getting to know the constructs of the language. Try stuff out in the simulator first to confirm correct operation before programming FPGA.
The Cyclone FPGA has differential line receivers built-in, and you use those by instantiating them in your design. My usual approach is to create a separate module that represents the "pad ring" for the chip, and instantiate them there.
You'll have two external pins for each logical signal used in the interior.
Best Answer
There are two ways of specifying PIN assignment — you can either use PinPlanner or
set_location_assignmentto specify the PIN along withset_instance_assignmentto specify the IO standard.I recommend you read I/O Management documentation from Altera. But here are few examples:
These are location assignments for 1 GbE RGMII Ethernet Interface:
And here is an LVDS clock input to FPGA:
Hope it helps. Good Luck!