Electronic – Merge a differential pair into one signal

fpgaintel-fpgaverilog

I have an LVDS ADC connecting to an Altera Cyclone IV FPGA. The data pins come in 7 differential pair channels, for a total of 14 pins.

Although each differential pair is physically 2 pins, my Verilog code expects only one signal for each pair.

How should I tell the FPGA that each differential pair should be merged into one signal for my Verilog code? Is this done in Verilog? Is this done in the contraints file?

Best Answer

The Cyclone FPGA has differential line receivers built-in, and you use those by instantiating them in your design. My usual approach is to create a separate module that represents the "pad ring" for the chip, and instantiate them there. You'll have two external pins for each logical signal used in the interior.

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Electronic – Specify exact pin locations on FPGA

There are two ways of specifying PIN assignment — you can either use PinPlanner or set_location_assignment to specify the PIN along with set_instance_assignment to specify the IO standard.

I recommend you read I/O Management documentation from Altera. But here are few examples:

These are location assignments for 1 GbE RGMII Ethernet Interface:

set_location_assignment PIN_D25 -to eth_tx_clk
set_location_assignment PIN_V6 -to eth_rx_clk
set_location_assignment PIN_D17 -to eth_rx_c
set_location_assignment PIN_G20 -to eth_tx_c
set_location_assignment PIN_M20 -to eth_reset_n
set_location_assignment PIN_E21 -to eth_rx_q[0]
set_location_assignment PIN_E24 -to eth_rx_q[1]
set_location_assignment PIN_E22 -to eth_rx_q[2]
set_location_assignment PIN_F24 -to eth_rx_q[3]
set_location_assignment PIN_J20 -to eth_tx_q[0]
set_location_assignment PIN_C25 -to eth_tx_q[1]
set_location_assignment PIN_G22 -to eth_tx_q[2]
set_location_assignment PIN_G21 -to eth_tx_q[3]

set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_c
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_c
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_q
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_reset_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_q

And here is an LVDS clock input to FPGA:

set_instance_assignment -name IO_STANDARD LVDS -to in_clk_100
set_location_assignment PIN_AJ19 -to in_clk_100
set_location_assignment PIN_AK19 -to "in_clk_100(n)"

Hope it helps. Good Luck!

Electronic – Adjustable clock in HDL

If you can tolerate 42 ns of peak-to-peak jitter (the period of your 24 MHz clock) in your synthesized clock, a direct-digital-synthesis (DDS) approach would probably be viable. This simply requires an accumulator register and an adder of the same width. The MSB of the accumulator becomes your synthesized clock.

You didn't say how much frequency resolution you need. To generate a 1 kHz output would require at least 15 bits in your accumulator; this would allow you to generate any frequency that's a multiple of 24 MHz / 2¹⁵ = 732.42 Hz. If you add more bits, you can get finer resolution. If you want ~1 Hz resolution, you'll need 25 bits, which would give you steps of 0.715 Hz.

For any particular DDS design, the number of bits in the frequency-setting value is the same as the number of bits in the adder and the accumulator. To change the frequency, even on the fly, just requires changing that value (but not its width).

Best Answer

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Electronic – Specify exact pin locations on FPGA

Electronic – Adjustable clock in HDL

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