I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag – there is no need to recompile the code). I came up with a solution which uses a counter and a comparator, the output of the comparator being the new clock but this idea creates a very ugly clock (spike) and I was wondering if there is a better solution to this.
On some fpgas (stratix) it is possible to use a reconfigurable pll but this doesn't apply to cyclone II unfortunately.
Thanks for your help
edit: Input clock 24 Mhz. Output clock 1khz – 10Mhz, clock is used for transceiver and receiver blocks, which are simply sending bytes between each other.
Best Answer
If you can tolerate 42 ns of peak-to-peak jitter (the period of your 24 MHz clock) in your synthesized clock, a direct-digital-synthesis (DDS) approach would probably be viable. This simply requires an accumulator register and an adder of the same width. The MSB of the accumulator becomes your synthesized clock.
You didn't say how much frequency resolution you need. To generate a 1 kHz output would require at least 15 bits in your accumulator; this would allow you to generate any frequency that's a multiple of 24 MHz / 215 = 732.42 Hz. If you add more bits, you can get finer resolution. If you want ~1 Hz resolution, you'll need 25 bits, which would give you steps of 0.715 Hz.
For any particular DDS design, the number of bits in the frequency-setting value is the same as the number of bits in the adder and the accumulator. To change the frequency, even on the fly, just requires changing that value (but not its width).