Electrical – Dealing with arrays in HDL

hdlverilog

(Assume Mux4Way has been already implemented)

/**
 * 4-way 16-bit multiplexor:
 * out = a if sel == 00
 *       b if sel == 01
 *       c if sel == 10
 *       d if sel == 11
 */

CHIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];

    PARTS:
    // Put your code here:
    Mux4Way(a=a[0],b=b[0],c=c[0],d=d[0],sel=sel,out=out[0]);
    Mux4Way(a=a[1],b=b[1],c=c[1],d=d[0],sel=sel,out=out[1]);
    Mux4Way(a=a[2],b=b[2],c=c[2],d=d[0],sel=sel,out=out[2]);
    Mux4Way(a=a[3],b=b[3],c=c[3],d=d[0],sel=sel,out=out[3]);
    Mux4Way(a=a[4],b=b[4],c=c[4],d=d[0],sel=sel,out=out[4]);
    Mux4Way(a=a[5],b=b[5],c=c[5],d=d[0],sel=sel,out=out[5]);
    Mux4Way(a=a[6],b=b[6],c=c[6],d=d[0],sel=sel,out=out[6]);
    Mux4Way(a=a[7],b=b[7],c=c[7],d=d[0],sel=sel,out=out[7]);
    Mux4Way(a=a[8],b=b[8],c=c[8],d=d[0],sel=sel,out=out[8]);
    Mux4Way(a=a[9],b=b[9],c=c[9],d=d[0],sel=sel,out=out[9]);
    Mux4Way(a=a[10],b=b[10],c=c[10],d=d[0],sel=sel,out=out[10]);
    Mux4Way(a=a[11],b=b[11],c=c[11],d=d[0],sel=sel,out=out[11]);
    Mux4Way(a=a[12],b=b[12],c=c[12],d=d[0],sel=sel,out=out[12]);
    Mux4Way(a=a[13],b=b[13],c=c[13],d=d[0],sel=sel,out=out[13]);
    Mux4Way(a=a[14],b=b[14],c=c[14],d=d[0],sel=sel,out=out[14]);
    Mux4Way(a=a[15],b=b[15],c=c[15],d=d[0],sel=sel,out=out[15]);
}

As you can see, this code looks quite inelegant. How can I deal with this repetitive code? I'm new to HDL, so I apologize for this trivial question. Is there the concept of loops (or something like it) in HDL?

Best Answer

In verilog you use a generate like:

   genvar i;

   generate

     for (i = 0; i < 16 ; i = i + 1) begin: muxes
          Mux4Way m(.a(a[i]),.b(b[i]),.c(c[i]),.d(d[i]),.sel(sel),.out(out[i]));
     end

  endgenerate

Related Solutions

Electronic – Converting 8 bit bmp to halftone bmp

Start by reading about "generate"

"Generate" will let you create lots of copies of a module with subtly different parameters. It can be a bit fiddly but it's better than creating a dozen copies of something.

However, that's not what you actually want to do here, because if you create a million copies of something you will run out of space.

What you want is a counter:

reg [31:0] var;
always @(posedge clk) begin
   if (var < limit) var <= var + 1;
   else var <= 0;
end

That roughly corresponds to a 'for' loop which will give you an incrementing value of 'var' on each clock cycle, until it hits the limit at which point it will start again from zero.

You'll find the whole thing easier if you store your pixels in an array (or RAM), and dither one pixel per cycle. Then it will take a million clock cycles to do your dithering, but your circuit will be small.

Remember, in Verilog everything happens in parallel, and everything loops forever.

Electronic – How does this direct digital synthesis accumulator work

Frequency modulation basically means that the frequency of the carrier is changed depending on the magnitude of the message (the audio signal). If the magnitude is positive, the frequency is increased. If the magnitude is negative, the frequency is decreased. Hence 'frequency modulation' because the frequency is being changed instead of the amplitude (AM) or the phase (PM).

In this case, a DDS is being used to generate the carrier wave. Direct digital synthesis basically involves outputting samples of a waveform from a lookup table at a specific rate. The rate is determined by a counter, called the phase accumulator. At every clock cycle, the counter is incremented by a little bit - the 'phase' accumulated by the carrier wave over the clock period. Generally DDS counters have a number of fractional bits so that the counter can accumulate a more accurate phase step on each clock period. It looks like this one does not have any fractional bits, probably because of the modulation and relatively high output frequency. After that, the output of the counter is fed to the lookup table, selecting a sample. A constant phase step will produce a constant frequency. However, adjusting the phase step by adding the message data will vary the frequency in lockstep with the message, forming an FM modulated signal.

This line looks like it is adding the audio message data to the phase step, but with some extra work to rescale it properly and deal with the sign bit.

Edit: Never mind, it does have 24 fractional bits. The lowest 24 bits of the accumulator are not used in the table lookup.

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