Electronic – SPI communication

spi

I am using TI's DSP 28335 to read data sensors using I2C, and SPI to send this data further to the FPGA. The device is set to use SPI in the slave mode with 8-bit data words, and I use interrupts.

I have read SPI wiki page, and various other documents (including TI's reference page for SPI), but I haven't understood the SPI communication.

So, the questions are :

  1. Is the slave device receiving all the time while the SS (slave select) is low?
  2. does the TX FIFO buffer always needs to be non-empty when SS is low? I have noticed that when TX FIFO buffer gets empty, some garbage is sent*.
  3. If the answer to 2. is yes, how to prevent it? Is setting MOSI to high impedance enough (by setting the TALK flag to 0)?

* Under garbage, I mean whatever is in LSB. Since I set data word size to be 8 bit, I expected the DSP to send only 8-bit data words from the SPIDAT register.

Best Answer

Yes, the slave will keep shifting one data bit in and out on each clock pulse as long as SS is low. When SS goes high the data which is in the shift register at that time will be latched.

A FIFO never needs to be full. It will accept a new byte of data the SPI master shifts in as long as it isn't full. As long as there's data in the FIFO you will read. When the FIFO is empty a read from it should return all zeros.

I would suggest you try to use the SPI in non-FIFO mode. FIFO mode is disabled by setting the SPIFFEN bit to 0 in the SPIFFTX register.

edit re your comment
There is no standard for what should happen if the master clocks new data in when there's none available; SPI doesn't occupy itself with you data content, it's basically just a shift register. The most sensible thing to do is sending zeros, but you could also be sending the last data from the FIFO again. Your protocol should avoid this kind of situation. Does the master really expect to read data, or is it only sending, ignoring data coming in? If it expects data, why isn't it there?

About the 8-bit format section 1.4.2 on page 17 says:

  • Data must be left-justified when written to SPIDAT and SPITXBUF.
  • Data read back from SPIRXBUF is right-justified.
  • SPIRXBUF contains the most recently received character, right-justified, plus any bits that remain from previous transmission(s) that have been shifted to the left.

This indicates that the full 16-bit shift registers are used, but that only 8 clock pulses are generated.