I got the impression from answers like this one that the the SS line for SPI is active low. Also from the wikipedia page.
However, I have a DS1305 real time clock. Pages 11, 12 indicate that the CE (chip enable) is active-high. Which I only noticed after I implemented it the other way, wondered what was wrong, and then re-read the datasheet.
There is no question that this device requires CE to be active-high. My question is, is that the normal polarity? Does SPI actually specify which way?
Best Answer
There really is no standard, and this is one of the reasons SPI is such a flexible protocol. Most devices I have seen have active low CS lines, assuming from past convention. For some reason Dallas Semiconductor chose to be different.