Electronic – SRAM isn’t blank on powerup, is this normal

digital-logicmemoryresetsramz80

I had finally finished my Z80 memory board, but I was disappointed to see that it wasn't working properly (simple NOP test with the address lines connected to some LEDs) as the counter quickly spiraled out of control instead of incrementing as it should. However, I am not one to give up and after about thirty minutes of continuity testing to unveil no short circuits and all proper connections, I finally thought to check if the SRAM chip was powering on with all 0s stored. I am well aware that SRAM (unless non-volatile, which my particular chip is not) will lose all of its contents upon losing power, but I had always assumed that it would be filled with 0's (ie "empty") when it regained power. The SRAM I'm using seems to be randomly filled with 1's and 0's each time the power is reset. It never remembers any data, but it isn't loading empty. This isn't really a problem as I can simply write a small program in ROM to load all 0's into RAM on powerup, although I would still like to know if this is how the SRAM should be functioning or not. Thanks!

Edit: I forgot to mention that after using the ROM to load 0's into SRAM the system worked fine, so this was indeed the issue.

Best Answer

Unless you have an initial state programmed, it will be more or less random. Although this may vary with different SRAM implementations. You also say "blank". Some might think that random is "blanker" than all 0's.

SRAM memory stores memory on back to back inverters.

simple sram

This forms a bi-stable system (two very stable states with metastability dividing them). So, upon power up the back to back inverters are briefly metastable.

This happens because as the voltage ramps up (from being turned on), both NMOS and PMOS of the back to back inverters would be 'equally' on, holding both bitnodes at half the supply voltage (this is the metastable state). Eventually some thermal noise (or any process that introduces variation) pushes or pulls this value down or up a little bit. At this point the bitnodes snap into one of their bistable states.

  • As an example, consider \$ Q=Q'=\frac{V_{supply}}{2} \$
  • Next, some thermal noise on Q increases the voltage up to \$ \frac{V_{supply}}{2} + \delta \$
  • Now, the NMOS feeding Q' gets turned on just a little bit more. And the PMOS feeding Q' gets turned off just a little bit more. So Q' pulls down from \$ \frac{V_{supply}}{2}\$ to \$ \frac{V_{supply}}{2} - \delta \$.
  • Next, since the voltage at the gate of the FET's driving Q node decreases, the PMOS turns on a little more (and NMOS turns off more). This causes Q to increase further to the supply. And this quickly snaps Q' to 0 and Q to 1.

In fact, there is even a paper "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers"

One very helpful plot contained in the paper is below. The dotted line represents the supply voltage ramping up:

metastability at powerup

  • On the left-side, everything is equal. In this case, random variation due to temperature or another number of factors bumps the bitnode into one state or the other.
  • On the right side, there is a bitnode which is skewed (purposefully or otherwise) to be much more likely to initialize in a particular state.

Depending on how each bitnode in the SRAM you are using currently was fabricated, you end up with more or less of one of the two situations above. In both cases, unless you intentionally skewed the SRAM, the initial outputs would look more or less random. In the left-hand situation, each subsequent powerup would generate more random patterns. In the right-hand situation, the initial startup would be seemingly random. But further powerups would cause the SRAM to tend to further certain states.

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