fpgapowerxilinx
From the results given by power analyzer, I find that the Xilinx FPGAs always have a high static power consumption no matter what your design is, although it will vary if your design utilize different number of resources.
What are the components consuming the static power on Xilinx FPGA reported by power analyzer?
My guess is:
interconnect (wires and switches) + slice used + IOB used + memory used + ASIC component used (multiplier, adder, etc)
What you need to do is to create a location map for the block with the DSP blocks. Jusy for your info, Vivado does not support UCF file format any more.
I cross posted this question on the Xilinx Forum here: http://forums.xilinx.com/t5/Implementation/How-to-determine-what-part-of-the-design-consumes-the-most/td-p/393247
This answer is largely based on the comments there. Thanks to Deepika, Sikta and Gabor.
First, enable 'Generate Detailed MAP Report' in the map process properties (-detail).
Then, open the Design Summary, and navigate to Module Level Utilization. Here is the complete hierarchy, showing exclusive and inclusive design utilization.
Each line will show a number pair like 0/5392. This means that that module contains zero of that specific element, but that module and all of its sub-modules contain a total of 5392 elements.
Here is my output (partially expanded)
When working on reducing the size, Gabor recommends switching to a larger FPGA in the synth tools so that it can completely map even when it's too large to fit in your current FPGA, and it will make the tools run faster.
Best Answer
First, it depends on the family. Older ones have less leakage.
Interconnect does have a lot of transistors, so it is likely high.
Slices used is high (for the logic) and low (the configuration logic is optimized for power since it doesn't need speed).
IOB is low.
Memory and ASIC components I can't comment on.