Specify Xilinx FPGA DSP placement with Vivado

fpgasynthesisxilinx

How can I, either in the RTL or in a constraint file, map specific DSP blocks to certain locations? I see that DSPs are labeled by site, with names like DSP48_X5Y30 and I'd like to be able to map a particular DSP instantiation to that site.

I have a design a tiled design where, without constraints, Vivado places things reasonably within columns but arranges the columns in what seems like a random order, creating very long routing delays. It's basically a systolic array, so the data flow is simple; manually mapping an instantiation to the correct DSP site should be easy. However, when I trace Vivado's automatic placement, it's not uncommon for two columns that are logically adjacent to be on opposite ends of the chip, with the next column being back near where the first column is, requiring an entire round trip across the chip to traverse three stages.

When I look online, I see manuals on how to do this with ISE, but everything I've seen related to Vivado involves pblocks, which seems like an extra layer of indirection which is pointless for something this simple?

Best Answer

What you need to do is to create a location map for the block with the DSP blocks. Jusy for your info, Vivado does not support UCF file format any more.

Related Solutions

Electronic – Using SVN with Xilinx Vivado

Xilinx create a YouTube video (sigh) to deal with this. Here is the link to the video

http://www.xilinx.com/training/vivado/vivado-version-control-overview.htm

Here is my summary of the video (8 minutes)

Before you start

If you really like full control, Xilinx suggests that you forgo the GUI entirely and do everything on the command line, and then you know what is source and what is not.

Otherwise, Xilinx realizes that Vivado projects are not designed for version control. DON'T CHECK IN THE ENTIRE PROJECT. But read on for hints...

Baseline

Of course, anything you write outside of the Vivado tool should be checked in.

Check in the the following files

*.v, *.vh, *.vhdl, *.edif  - HDL and Netlist
*.xdc - Constraints
*.xci - IP Core
*.bd  - IP Integrator Block Diagram
*.xmp - Embedded Subsystem
*.sgp - System Generator Subsystem
*.bmm
*.cdc - Chipscope
*.elf
*.mem

IP blocks

If you use IP blocks, generate the IP in a unique folder, and check in everything.

Checkpoints

If you want to be able to rerun parts of the flow without running everything, check in the checkpoint files.

*.dcp - Design Checkpoints

My Addendum

If Xilinx tools were efficient, I wouldn't recommend checking in the dcp files, but they take so many hours to run, it might be worthwhile at the cost of an ugly version control system.

The video doesn't say squat about the Vivado project files (*.xpr) so here is my suggestion:

*.xpr
*.data/*/fileset.xml
*.data/*/runs.xml

The alternative that Xilinx recommends (which is really a hack, not suitable for version control) is to run the File -> Write Project Tcl command each time you want to commit, and then commit that TCL file to version control. When you update your local folder, you need to rerun that TCL file to create all of the project files. Yuck.

Electronic – Static power of Xilinx FPGA

First, it depends on the family. Older ones have less leakage.

Interconnect does have a lot of transistors, so it is likely high.

Slices used is high (for the logic) and low (the configuration logic is optimized for power since it doesn't need speed).

IOB is low.

Memory and ASIC components I can't comment on.

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