I have four TTL level signals that must change state in a particular order.
From the “go” signal on one of the lines, all toggling of the other lines will be done within 100 us. The other three signals will toggle at most a couple of times. The start, end and duration between state change that these other three signals will toggle varies depending upon metrics in the system that are know well before the go signal occurs. But the timing is variable so the sequence of pulses and their durations need to be programmable. The timing and duration is known before the sequence starts.
Here’s the rub, I need sub microsecond jitter accuracy. The 120 MHz ARM micro I’m using can’t guarantee such deterministic timing profiles due to pipelining and a host of other performance enhancing reasons. We can do our best to architect the system to minimize the jitter but I want to know if it’s use a faster micro or DSPs or CPLD, PALs, etc. are a typical way to get the accuracy and resolution I’m looking for.
In the past with an 8 bit micro running at 8 MHz with one instruction per clock cycle I could write some assembler, put the micro to sleep, wake on interrupt, count some clock cycles and have 0.25 us accuracy
What technology to I need to investigate to achieve this resolution and accuracy?
Best Answer
It's not clear what exactly the signals are you need to generate, and their timing relative to incoming signals.
However, 250 ns isn't really all that hard to achieve with something like a EP series dsPIC, for example. At 70 MHz instruction rate, that gives you up to 17 instruction cycles of allowable jitter. That's a lot.
Having your incoming signal cause a interrupt, then generating the output signals from fixed instruction timing will give you much less than 17 cycles of jitter. It would be even better if the input signal can trigger a PWM generator or the like. But, you haven't given enough information about the nature of the output signals to know whether specific hardware available on such micros would be applicable.