Electronic – Target of concurrent assignment or output port connection should be a net type

I am trying to implement Fast Fourier Transform in Verilog for 32-point sample and have written the following butterfly module:

module bffly(
input wire signed [15:0] xa_r,
input wire signed [15:0] xa_i,
input wire signed [15:0] xb_r,
input wire signed [15:0] xb_i,
input wire signed [15:0] w_r,
input wire signed [15:0] w_i,
output reg signed [15:0] ya_r,
output reg signed [15:0] ya_i,
output reg signed [15:0] yb_r,
output reg signed [15:0] yb_i,
output reg ready,
input wire clk,
input wire enable
);

// ya = xa + xb*w
// yb = xa - xb*w

// ya_r = xa_r + xb_r*w_r - xb_i*w_i
// ya_i = xa_i + xb_r*w_i + xb_i*w_r

// yb_r = xa_r - xb_r*w_r + xb_i*w_i
// yb_i = xa_i - xb_r*w_i - xb_i*w_r


wire signed [31:0] temp_r_32;
wire signed [31:0] temp_i_32;

wire signed [15:0] temp_r_16;
wire signed [15:0] temp_i_16;

assign temp_r_32 = xb_r*w_r - xb_i*w_i;
assign temp_i_32 = xb_r*w_i + xb_i*w_r;

assign temp_r_16 = {temp_r_32[31], temp_r_32[28:14]};
assign temp_i_16 = {temp_i_32[31], temp_i_32[28:14]};

always@(posedge clk)
begin
 if (enable)
 begin
    ya_r <= xa_r + temp_r_16; 
    ya_i <= xa_i + temp_i_16;
    yb_r <= xa_r - temp_r_16;
    yb_i <= xa_i - temp_i_16;
    ready <= 1;
 end

 else ready<= 0;
end

endmodule

The butterfly module is working properly. I have checked it with th test fixture.

In the fft module, I have made several calls to the butterfly module. Here is a code snippet of the fft module:

module fft(
 input enable1,
 input clk,
     input [15:0] a0,...,input [15:0] a31,
     output [15:0] br0,..., output [15:0] br31,
     output [15:0] bi0,..., output [15:0] bi31, 
     output wand ready,
     output wan enable3
);
wire [15:0] wr0, etc. stores the twiddle factors.
reg [15:0] tr0;...,reg [15:0] tr31;
reg [15:0] ti0,...,reg [15:0] ti31;

bffly z12(.ready(enable2),.clk(clk),.enable(enable1),.xa_r(a3),.xa_i(16'b0),.xb_r(a19),.xb_i(16'b0), .w_r(wr0), .w_i(wi0),.ya_r(tr24), .ya_i(ti24),.yb_r(tr25), .yb_i(ti25));
bffly z13 (.ready(enable2),.clk(clk),.enable(enable1),.xa_r(a11),.xa_i(16'b0),.xb_r(a27),.xb_i(16'b0), .w_r(wr0), .w_i(wi0),.ya_r(tr26),.ya_i(ti26), .yb_r(tr27), .yb_i(ti27));

For all such calls to the butterfly there is an error as follows:

Target tr24 of concurrent assignment or output port connection should be a net type.

Target tr26 of concurrent assignment or output port connection should be a net type., respectively

When the target is assigned as a wire and not as a reg, then it works fine.

What do I do in this case ??