There are 2 reasons for using an RC end termination topology. (can only be used on signals with 50% duty cycle such as - clocks)
- Reduce power consumption
- Centering the eye diagram.
If you do not care about either of these then a single far end resistor will do. (screw the cap) and you can end the resistor to either Vcc or Gnd.
If you do care, then connecting the capacitor to either Gnd or Vcc should be fine. The capacitor will appear to be a short circuit during the edges, which is what you want and the average voltage between the capacitor and the resistor would be 1/2Vcc, which reduces your power.
It's not the frequency of the signal that's sent down a PCB trace, but the risetime that's important.
A 21cm PCB trace is about 30cm 'air equivalent', and as the speed of light is 1nS/ft (in units convenient for the engineer), that's about 2nS round trip. If the output gate risetime is longer than this, and most modern 'low speed' MCUs and SoCs will have either slow drivers, or drivers that can be selected slow/fast for just this reason, then there is no need to add extra series termination.
A 33MHz signal has a 30nS period, or 15nS high and low. A signal of this rate could get away with >2nS risetimes, as long as the receiver could cope with that and meet tsu and th times. Check the documentation of your MCU to see if risetime or drive strength (selectable low output current) is specified.
Even if the output impedance is not specified, it may be possible to infer it from drive current/voltage graphs, or output voltage specified at multiple currents in the electrical characteristics tables. Failing that, you could measure it by loading an output with various resistors and measuring the output voltage drop.
The usual assumption about driver output impedances is 'around 10 ohms'. It's difficult to make them much less, and much more and they won't meet dynamic high/lows for logic. In the absence of more information, a series termination resistor of 'several tens of ohms', so 33 or 47 ohms is not uncommon. If you you err, erring lower rather than higher is probably better. The board trace Z0 is unlikely to be lower than 50 ohms or higher than 100.
Once you have a series resistor there, the best way to tune it is to use an oscilloscope, but it will need to be a fast one, you need to be able to see <2nS features. A scope this fast will have a 50 ohm input impedance, and you'd use a 1k resistor tapped onto the line as a probe. This gives you a nice pot down into the scope, and very low capacitance tap point to measure with.
Bear in mind that a series resistor can only be used for single-point receiver at the end of the line. If the several receivers are spread out down a trace, a series resistor is the worst thing you can do, this configuration needs a low impedance driver, and a matched termination at the far end of the line.
Best Answer
Signal integrity headaches due to termination and reflections in transmission lines do not depend on the frequency of the signal. The crucial factor is the slew rate (or rise time), which determines the highest frequency in the bandwidth of the signal. Here is a random example from the internet:
Such ringing on the edges may cause one clock edge to be interpreted as several clock pulses by the receiving chip, which will corrupt your transmission. This only depends on rise time, not signal frequency: a 1Hz signal with fast ringing edges can do this too. Edges that are too slow are a problem too. Your 74VHC chip datasheet specifies a minimum input transition rise/fall rate of 20-100 ns/V depending on supply voltage. If the signal spends too much time in the transition zone, this can cause problems.
74VHC rise time is listed as 2-3 ns, which could cause problems considering the length of your cable. However, its drive current is quite low (4/8 mA for 3.3V/5V), which in your case is excellent as the chip's weak output drivers will behave more or less like a "free" source termination resistor which should be sufficient to avoid any problems.
With a 74AC or LVC chip, it would be another story, these would require a source termination resistor.
Make sure to place a decoupling cap on the cable driver chip's power pin. It needs transient current to charge the cable capacitance. Bad decoupling will cause crosstalk through the power supply, or transient supply voltage (and output voltage) sag when many outputs switch simultaneously.
You can check signal integrity at the receiver end, but make sure you use a 10x probe of adequate bandwidth and the tiny ground spring (not the alligator clip lead).
Note that you should probe at the receiver! Signal will be distorted at the driver (pic source):
Voltage at driver side ("A") plateaus halfway between logic levels during the whole time it takes for the signal to make a roundtrip in the transmission line. During this time, line capacitance is being charged, so the driver draws current to charge it. However, signal at the receiver end is clean, and its rise time does not depend on transmission line length and total capacitance (besides losses). This is a bit counter-intuitive, but it works. Driver supply current does depend on line length and capacitance though, as the current to charge the line capacitance comes from the supply.