Digital Signal Processors can do the FFT in real time. They have a particular architecture which means that certain instructions (MAC - multiply accumulate) can be done very quickly.
But then this turns in to an embedded software project too as well as the electronics design, if you're ok with that.
You can get development boards from companies such as Texas Instruments which contain a processor and break-out box arrangement for experimentation.
The OP-AMP proposed is a MCP6V07 with an input noise density of around 60 nV / \$\sqrt{Hz}\$ - I've kind of averaged this in my head across the range that your circuit seems to work i.e. DC to about 16kHz. It's 16kHz because of the 100 ohm and 100nF low pass filter on the output of each op-amp.
What noise does this mean in reality? Well, other people cleverer than me have said that if the filter is a simple single order low pass filter then you better consider 1.6x the cut-off frequency for the true effects of noise so, that's a bandwidth of about 25kHz - now take the square root and you get 158. Multiply that by 60nV and the equivalent input noise due only to one op-amp is about 10 microvolts RMS. There are two op-amps each with the same noise and these noise will add to give 3dB more noise i.e. about 14 microvolts RMS into your ADC if the gain of the Op-amp circuit were unity.
Compare this with an AD620 - it has two quoted figures; input noise and output noise. Input noise is 9 nV/\$\sqrt{Hz}\$ and output noise is 72 nV/\$\sqrt{Hz}\$ so immediately there is a benefit to using the MCP6V07 but waiiiiiit....
.... Will the circuit gain be unity or is it more likely to be ten? If it's a gain of ten then the INA wins hands down because its output noise remains at 72 and is added vectorially to its input noise x10 - this would be a figure of \$\sqrt{90^2+72^2}\$ nV/\$\sqrt{Hz}\$ = 115 nV/\$\sqrt{Hz}\$.
The op-amp (on the other hand) would be a lousy \$10\cdot\sqrt{60^2+60^2}\$ nV/\$\sqrt{Hz}\$ = 848 nV/\$\sqrt{Hz}\$.
These last two figures are output noises of course because I've multiplied them by my assumed gain of ten. If the gain is different then you now, hopefully, have the math to work it out. If you could decide on what circuit and gain value then you are in business - I've just compared devices.
Back to assuming a gain of unity and the op-amp circuit - 14 microvolts of noise into your ADC - talking of which, I opened the data sheet on the C8051F350 but it appears to be longer than the koran and bible back to back so, given that you have an anti alias filter of about 16kHz which pretty much excludes noise above 25kHz (say) I am willing (but not overly excited) about making the assumption you are sampling at 50kHz - if it's a lot less than this then sort out the 100 ohm and 100nF and make them more reasonable.
Assuming that you will measure the full 14 microvolts of noise and that your FSD input is (say) 2.5 volts, you can make a rough estimate of signal-to-noise ratio. The sinewave needed to generate a FSD of 2.5 Vp-p is 0.88V RMS.
This means your SNR is a measly 96 dB - yet you are using a 24 bit device. 96dB is about an ENOB is 16 bits (rough, head calculation)
If you want close to 20 bits ENOB you are going to have to vastly improve the interface circuit.
Best Answer
It is called a digital ramp ADC.
The specific ADC described by the OP does not have a sample-and-hold and relies on the input signal being steady but there is no reason it couldn't have one. It just compares the input signal to the output of a DAC with a comparator, and it ramps up the DAC value and whenever the DAC output just exceeds the ADC input, it latches the DAC input to the ADC output. Then it restarts the ramp. As a result, it has latency that varies based on the input value which is not a desirable trait.