When we wish to add timing constraints to our design in TimeQuest Timing Analyzer, we have two options. We can use either a post fit netlist or post map netlist. Post map netlist is available after mere design synthesis, however the post fit netlist is only available after fitting.
Now my question is which is used when?
Is it true that post fit netlist has timing information but post map does not? Besides that, when comiling an FPGA design, is post map netlist defined using the "atoms" of the FPGA?
Best Answer
The process of mapping implements the specified behavior in the selected technology, but does not assign specific physical resources to the individual elements (e.g., LUTs and FFs). Simulation at this level models the gate delays fairly accurately, but uses statistical averages for the wiring delays.
The process of fitting allocates the specific physical resources for each design element identified during the mapping stage, and also allocates the routing resources required to make the connections. Simulation at this level gets both accurate gate delays as well as wiring delays.
Since fitting is a fairly compute-intensive process, and since post-map simulation is about 90% of the way there in terms of overall timing accuracy, many designers do the bulk of their timing verification using post-map timing.