I am writing a controller for a low power/mobile DDR module on my FPGA. To allow debugging, I use a functional model written in Verilog. In it, the setup and hold time for some signal is set to 1.5 ns. If I understand everything correctly, this means that the signal can not change 'within' 1.5 ns of a rising clock edge.
However, the RTL that I've written does not include timing, so the signal appears to change instantly, yielding hold time warnings.
On the one hand, I am not too concerned; I'm only getting warnings, and I think that during a project for my university, we were told to simply ignore these errors.
On the other, I don't like to ignore warnings. The manufacturer would not have implemented these warnings if they have no purpose. Since Xilinx ISE is able to check timing constraints, I feel like it should be possible to route and map my design, and use the generated timings somehow (but maybe I'm making things too simple here).
I'm sure there are more people with the same problem. What is the proper way to deal with these warnings?
Edit: On this page, I found some more information. You can generate a post-map or post-place-and-route simulation model. I suspect this includes the timings. However, it seems only modelsim can actually perform the simulation.
Clarification: Ideally, I would be able to synthesize (or at least get as far in the process of generating the layout as possible) my part of the design (I have the RTL and I have specified the board, so I think this should be possible), then combine it in a testbench with the functional model to test if my design has the proper timing delays. However, I can't make this work in Xilinx ISE 14.7.
Best Answer
As dave_59 pointed out, timing checks on RTL are not very meaningful. That said, here are 4 possible approaches:
`ifdef ... `endif) around your timing checks; timing checks disabled with RTL<=) to<= `D, where`Dis a your delay (ex`define D #2)`Das empty (aka`define D)$setuphold( D, CLK &&& actiming_enable, tSETUP, tHOLD);