Xilinx tools give LOTS of warnings on any significant design. Sometimes, I go through fudging my design to remove warnings (like if one channel from an ADC module is unused, I go change the module to remove it, etc). However, I'd really prefer to be able to keep my design blocks fixed and logically complete (more reusable), and just mark the unused signals as "that's fine, I know about that, go ahead and do your thing (remove them)".
It's also much easier to understand say a 16-bit shift register if I can use a 16 bit signal, instead of for example a 13 bit signal in the case of always loading "00000" in the LSB bits. I've been obfuscating my code to remove these warnings.
Stupidly, marking outputs specifically as 'open' is still a warning… although that's obviously the design intent.
Is there any attribute or UCF entry or anything that I can use to suppress these specific warnings but only for specific signals? (unused signal, signal always '0'/'1')
EDIT
I just discovered project message filtering. With that, I can mark specific warnings as hidden (using the complete text). This is close enough, I suppose… although I'd still like a way to prevent them from being generated in the first place.
Best Answer
I had this same problem for a long time. Unfortunately there is no good way to change some warnings into info's or some errors into warnings. My problem was that some warnings should have been errors! Some of my FPGA's were generating 5000+ messages and there was no way to wade through them to see which ones were important or not.
In the end, I wrote a program that would read a Xilinx log file and reassign warnings/errors/infos depending on my custom settings. Works great. Too bad I can't make that program public.