The most tedious thing for me while routing PCBs are the powers. I have made several PCBs of these kind and it seems that I have not learned much from the process. The power connections are always a mess.
Here is the description: The circuit need multiple powers including \$\pm5\,\mathrm{V},\pm12\,\mathrm{V}, +3.3\,\mathrm{V}\$. The circuit is to measure weak current at \$10\,\mathrm{pA}\$ level. Therefore, the PCB layout is supposed to be very important. And the ICs are placed in different places which may need different voltages. A four layer PCB is used with signal/ground/\$+15\,\mathrm{V}\$/signal. I can give \$+15\$ and GND for ICs directly through vias. However, for \$\pm5\,\mathrm{V}, -12\,\mathrm{V}\$ and \$3.3\,\mathrm{V}\$, the power lines keep messing with each other. Sometimes I have to use several vias in one power line. Further, if a STAR structure is to be used, the condition will be much more complex.
Could I ask for some tips on design of the power lines? And how to improve my PCB skills?
supplement: Many experienced engineers talked about analog ground and digital ground. Here comes a perfect tutorial for me: http://pdfserv.maximintegrated.com/en/an/TUT5450.pdf
And about decoupling techniques for analog IC, here is a very good one: http://www.analog.com/static/imported-files/tutorials/MT-101.pdf
Best Answer
Generally you don't need separate planes for power. If you have a good solid ground everywhere (you do want a plane for that in many cases), then the only issue for power is that the voltage drops due to the power current and DC resistance in the traces are acceptable. Don't worry about high frequency AC impedance in delivering power that much. Instead, bypass the power locally to the local ground at each place it is used.
In fact, especially for sensitive analog circuits, I often add a little deliberate impedance to a power feed so that a local capacitor has something to work against to filter out the high frequencies. If you put a 0805 chip inductor, for example, in series with the power connection of each IC, then follow that with a 20 uF ceramic cap to ground, you will have clean power everywhere. This is for chips and individual circuit sections that draw up to a few 10s of mA.
I just checked, and the jellybean 0805 chip inductor I commonly use for this is 950 nH and 600 mΩ. Just about any reasonable copper power trace will have less inductance and resistance than that. With this extra impedance in series with the power, a little more due to the power trace doesn't matter. With this strategy, allocating a plane to a particular power net it just a waste of routing space, and doesn't produce as good a result anyway.
As I have said many times before here, another important thing to do for low noise is to keep local high frequency currents off the main ground plane. The ground connections of a noisy subcircuit are all tied together with a local net, then that net connects to the main ground plane at a single point. The same thing works in reverse to keep noise from getting into a circuit. A sensitive analog circuit should also have its grounds connected locally, then that net tied to the main ground plane at one point.