I have to interface a video format converter with a ADC IC, which converters RGB analog data to digital. The connection between this ADC and Converter is a 20 bit data bus which clocks at about 170MHz. Since I have the PCB area constraints I cannot perfectly match the trace length of this data bus. I heard that there are matched trace length tolerances depending on frequency so that it will not damage the signal acquisition by the destination.
My question is how to calculate trace length tolerances in a High Speed PCB design? (in differential pair routing and high speed data bus routing)