First, as you mention, the critical parameter is usually the rise and fall times of your edges. You can estimate the effective "frequency knee" of your signal by
\$ f = \dfrac{\alpha}{t_r} \$
where \$t_r\$ is the faster of your rise and fall times. The parameter \$\alpha\$ is a kind of fudge factor; it depends on whether you measured the rise time as a 10%-90% or a 20%-80% value, and some authors give numbers between 0.5 and 0.8, but to be safe you could just use 1.0.
As Jippie discusses in his answer, if the wavelength associated with this frequency is more than 10x the trace length, you generally don't need to worry about transmission line effects.
And in fact this is just how most CMOS and TTL drivers are intended to operate---except for certain specific types, they don't really have the current drive capability to drive a termination resistor of 50 or 75 Ohms.
Another complication is that most CMOS and TTL devices won't have a spec for rise and fall time. You'll have to estimate it from the drive current capability and the load capacitance:
\$ t_r \approx \dfrac{(V_h-V_l)C}{I}\$
Where I is the short circuit output current for your driver and C is estimated from your track geometry and the input capacitance of the load.
If you are using ECL parts, be aware that even if you don't terminate the transmission line, they still need a pull-down resistor to properly bias the output transistor.
Looks good and you may just get lucky with that layout.
Being an engineer, luck is usually not a method I rely on :-) So let me show you what I would do:
1) Define the PCB stackup. Looks like you are on a 4-layer stackup, but we need to know material and thickness of laminate/prepreg etc.
2) Calculate trace widths to give you 50R on all layers. Your traces looks wide, but you didn't give your stackup so they may be okay. I would worry a bit about crosstalk though if those traces really are 50R (because I then know that they are far from your reference plane, which increases crosstalk).
3) Engineer a great low impedance power delivery network (PDN). I read between the lines that you have two planes for power and ground - which is a really good idea. I would use my tool at pdntool.com to select the right capacitor combination. And use the knowledge that bypass capacitor location is fairly unimportant. So the caps would be placed last so the don't interfere with the routing.
4) Repeat this for your Vtt supply. The termination voltage is being constantly pulled in both directions, so it needs a low impedance as well. With DDR1 on a low layer count board, Vtt ripple is a common problem (and make sure Vref is not connected to Vtt!!!). This would usually require a Vtt island with sufficient bypass. Remember about half the ripple on Vtt will be present as noise on top of any input signal terminated to Vtt.
5) Do some quick IBIS simulations to find a trace separation that gives you acceptable crosstalk. Use Hyperlynx, SigXplorer or some such tool for this. Or get someone to do it for you.
6) Do your timing analysis to find the acceptable tolerance on trace length matching (don't overdo length matching - just keep within your calculated tolerance).
7) Document the above in a nice document and call a peer review - this is a great time to find errors. You could also post that here and ask for problems in your reasoning.
8) Enter everything as routing rules in your CAD tool and do that layout. Remember with a well engineered PDN and 50R on all layers your via count is irrelevant. Also if you just route your differential clock as two 50R traces of same length (within half a rise-time or so), you need not treat them special.
For inspiration you can also look at the layout examples on the JEDEC website.
Hope this helps - feel free to ask more questions.
Best Answer
Length matching is about timing so if you want to know how tightly you have to length match you have to understand the timing budget for your interface. Signals will leave your source, and arrive at your destination with some timing relationship. Your receiver requires a certain timing relationship between clock and data in order to be guaranteed to function correctly. This is usually defined as setup and hold time, or how long before the clock edge your data needs to be valid, and how long after it must stay valid.
There are several things in a system which eat into this budget, one of which will be your routing. Sometimes a manufacturer will tell you this information, other times you must derive it from the input and output timing data of your transmitter and receiver. Of course it's easy to just say well I must match exactly, because then you don't have to think about it :)
But let's think about it for a minute. You have a 170Mhz signal? That's a period of 5.882ns. What would happen if you routed all your data to within one inch of clock. What would be the worst case timing difference. Propagation time for a top layer trace, a microstrip is about 150ps/in. So a 1 inch difference will skew a data signal from clock +/- 150ps. That's really not bad at all considering your 5.882ns clock period. In fact 170Mhz is really not that fast.
If you understood the output skew from your transmitter, and your setup and hold times for your receiver you could come up with a number for the acceptable routing delay. Of course there are other factors, clock jitter, ISI, etc, but this should give you a good idea of what you can do.