Electronic – Tuned common emitter amplifier design

You should use \$25(\beta+1)/I_C\$ for the input impedance; the base current also flows through the emitter in addition to the collector current.

Also don't forget that the 25mV figure is an approximation for the thermal voltage; the textbook seems to be using 25mV, the same as you, but a more accurate figure is 25.85mV.

It's late here, so I will write a little but will have to add more after I get back up in the AM....

Usually, you know what your \$V_{cc}\$ is. And you know what you want to use as the quiescent collector current, \$I_q\$. I don't agree with your web pages about setting the DC point for \$Q_1\$'s collector, though. Instead, I generally want the DC point for the emitter to be at least \$1V\$ above ground, to aid temperature stability due to the emitter's little-re (\$\frac{k\cdot T}{q\cdot I_C}\$) dependence on T. More is better. But I shoot for \$V_e \ge 1V\$ as \$V_{CC}\$ allows. I also know that to stay well out of saturation, I want \$V_{ce} \ge 2V\$ at all times. So I've already eaten up \$3V\$ of headroom, before I've started. So I take \$V_{c_{q}} = \frac{V_{cc} + 1V + 2V}{2}\$ as the quiescent voltage for the collector. For example, if \$V_{cc} = 10V\$, then \$V_{c_q} = 6.5V\$; not \$5V\$ as your lessons would seem to have you do. This provides \$\pm 3.5V\$ collector swing. \$5V\$ is just too low and squeezes the BJT too tight and leaves nothing for temperature stability. It works fine if you have lots of headroom. But with low headroom, everything starts to matter.

From \$I_{c_q}\$ I can estimate \$V_{{be}_q}\$ and from that I can estimate the operating point for \$V_{b_q}\$, knowing that I've set \$V_{e_q} = 1V\$. Also, of course, it's easy to calculate \$R_c\$ and \$R_e\$, too. And I can also estimate \$I_{b_q}\$ and from that I can figure out the divider needed for the base. This is all discussed on your DC Conditions page.

So let's do a full-up DC design to start, using \$V_{cc} = 10V\$ and \$I_{c_q} = 2.5mA\$:

^{simulate this circuit – Schematic created using CircuitLab}

I hope you can figure out where the values came from, given that you accept where I set the voltages and picked out the quiescent collector current.

The reason, again, for \$R_e\$ is because there is, in effect, a tiny, temperature dependent thermal voltage at the tip of the BJT emitter. If you take into account \$I_c\$, then this is converted into a tiny, temperature dependent resistor value often just called 'little-re'. Regardless, you want to overwhelm the thermal variations there with something. Since the value of \$\frac{k\cdot T}{q}\$ is on the order of \$26mV\$, jacking the emitter up to about \$1V\$ makes the thermal voltage tiny by comparison, so when it varies a bit over temperature it doesn't affect the emitter's operating point very much. So that's why it's there.

Ah. You thought perhaps that it was there because of the DC gain I might have wanted? No. It's there to set the DC operating point for thermal stability. Of course, yes. The gain here is terrible. It's \$\frac{1400}{400} \approx 3.5\$. And I can't really change it, either, if I want to keep my thermal stability and keep the transistor well out of saturation, etc.

In short, I'm trapped. No wiggle room, at all. That's not so good.

Luckily, AC comes to the rescue. let's say the new schematic looks like this (I'm still leaving out C4. For these purposes, it's just not necessary and I'll let you worry about it on your own):

^{simulate this circuit}

The input is AC. The emitter of \$Q_1\$ will follow that input with slightly less than a gain of \$1\$. If \$C_2\$ is large enough in value, then it will essentially be a short circuit (or wire) and won't impact the impedance of the \$R_{ac}\$ leg. So, at AC, you can see that the effective AC impedance of the entire emitter load is \$R_{ac} \vert\vert R_{dc} \approx 58\Omega\$. Now, the gain is more like \$\frac{1400\Omega}{58\Omega} \approx 24\$. And we get control over the gain at AC. But at DC, the emitter is still sitting high up, at around \$1V\$ where we want it.

So we get to have our cake and eat it, now.

There are two perspectives shown on your web page:

Either works. The difference is that the left side topology allows you to easily set the AC gain-setting resistor more directly, as the capacitor ends up bypassing the other, DC-setting, resistor. However, this forces you to divide out the DC resistance needed to set the emitter voltage, so that becomes a little more complicated. The right side topology makes setting up the DC resistance for a given emitter voltage and quiescent current trivial. But it makes the AC gain resistor's value a little more complex to work out since you have to treat it in parallel to the DC setting resistor. It's just two different ways of approaching the same thing.

There are also some bootstrapping techniques I hope you also learn about. The simplest uses the fact that the emitter follows the input at a gain of about \$1\$ to actively drive the base's resistor divider node and where the signal directly drives the BJT base, with a new resistor now between the divider node and the BJT base. The capacitor develops an equilibrium voltage across it that is just enough to make up for the difference across it. And since one side of that new resistor is driven by the signal itself and the other side is driven by a low impedance emitter that is following the signal pretty well, the new resistor itself sees the same voltage (DC bias plus AC) on both sides, so almost no current flows. And this very much increases the input impedance. Which is nice. And there are other improvements, as well.

Here's an example of a simple bootstrap:

^{simulate this circuit}

(Take note that I switched over to the other emitter configuration we've discussed here, just to do something different.)

The idea is that the signal directly drives the transistor base through \$C_1\$ and also that signal is on one side of \$R_3\$. \$R_3\$ is a DC path to allow \$C_1\$ to find its equilibrium state voltage and as a DC path for \$Q_1\$'s starting up the required \$V_{be}\$ to put \$Q_1\$ into the active region. \$C_4\$ picks up the low-impedance copy of the signal at the base (so there is some current drive available) and drives that back to the divider node. Now, slight variations in the signal will move \$Q_1\$'s base up and down, and these will be copied across to \$Q_1\$'s emitter, which will then drive those same changes back to the divider node. Assuming that \$C_4\$ has exactly the right voltage across it (given enough time, it will) to exactly match the difference between the quiescent emitter voltage and the quiescent divider node voltage, then all this works fine. The divider node will move up and down, driven by the emitter which is copying the base, and the other side of \$R_3\$ will be also moving up and down roughly in phase, as well. So \$R_3\$, if everything were perfect (and it isn't), would have the exact same voltage across it and would then have no current flowing in it, at all. The reality is that the emitter does have a copy, but at a gain slightly less than \$1\$. And capacitors, even largish ones, will add a slight phase difference. Etc. But it works pretty good just the same. And it greatly reduces the load on the signal source.

And in any case that is only the beginning. Practical amplifier stages can and will take into account a lot more than all this.