Electronic – Understanding LDO Dropout

This all depends on the frequency of current draw of the device on the line, the frequency response of the capacitors used, their ESR, parasitic inductance of traces joining capacitors and loads and actual physical layout. The purpose of decoupling capacitors is to provide a local power source for the load and keep the voltage rail clean (these two are different ways of saying the same thing, effectively).

Placing individual capacitors physically close to the IC they are supposed to be decoupling minimises trace inductance and hence maximises their suitability for purpose - so the fact that you have three capacitors all on the same line adding up to ~2uF doesn't mean that you could replace the three with one 2uF capacitor and have it act exactly the same - each is connected to the next via a small resistor and a small inductor representing the impedance of the copper between the two.

How much ripple can you tolerate on the power rails? If you know this you can measure existing ripple under worst-case conditions, remove a capacitor of your choice and repeat the measurement. If that takes you out of specification - put it back! Don't forget that you will need to repeat this measurement at each of the ICs you have with the shortest possible ground lead for the 'scope. You should be able to get hold of some ground springs like the one shown below to help this. If you use the standard lead you get with the scope, you will be measuring with its inductance in place too which will make your measurements pretty much meaningless.

So what should you do? Well, if it were me I would leave the existing caps in. They cost almost nothing and aren't likely harming anything. If you really need to remove one or all, then do it using the approach I have described.

Most LDOs can't sink any current, only source.

This is a simplified schematic of an LM317.

The NPN output stage can only source current, it will become reverse biased if it is required to sink current. Other LDOs have PNP output stages but they also can't sink current, probably until the output voltage goes above the input voltage.

If you have a static load on the supply rail (more than 19 mA in your example - say a 220 ohm resistor) then it may not be a problem as that static load will sink the fault load.

The other thing I have done is put a zener across the clamp supply to provide path for the fault current, a 4.7V zener may be appropriate.

Even if you don't have external diodes most CMOS logic devices have diodes just as you have drawn but internal to the device.

Voltage references often have output stages that can source or sink, but they are too expensive to sue in this type of application.

An active clamp such as below may meet your needs, it won't inject any significant current into your supply - the current will pass through the PNP transistor to ground.

Does the input resistor have to be 1K? Can it be higher? That would reduce the current you have to divert.

^{simulate this circuit – Schematic created using CircuitLab}