Electronic – Unrealistic ESR calculated from DF

This is hard to answer without knowing the what exactly is going on inside the control loop, which is probably not described with much detail in the datasheet. Saying it is "optimized" for 30 mΩ doesn't say what it really needs or what happens when it's not exactly 30 mΩ. Since they make a issue of the output cap ESR, there should be a min/max ESR spec elsewhere in the datasheet.

Hopefully 0 ESR is OK, else it gets inconvenient. Lower ESR is generally better, and certainly closer to ideal, for a capacitor. Capacitor spec sheets therefore often only spec maximum ESR. In that case you either have to get the guaranteed minimum from the capacitor manufacturer, or add deliberate resistance. A better answer is to stay away from chips that specify a minimum output cap ESR to be stable.

That chip is probably old, as ceramic capacitors have come a long way in the last few years. These have much lower ESR than tantalum, and can now approach such capacitances at reasonable cost. Newer chips now make use of the lower available ESR to get better performance instead of requiring the capacitor to have a high resistance. This is a all around better strategy.

Personally, I would stick it on my LCR bridge, set it for 120Hz or 100kHz (as appropriate) and the appropriate equivalent circuit, and read off the C and R from the digital displays. That's pretty accurate down to about 20m\$\Omega\$ ESR. This is how it works:

The connections to the DUT are made Kelvin-style with four coaxial cables.

The complex (both real and imaginary parts) of ratio of the voltage/current gives the complex impedance, from which the C and ESR can be calculated. The former are found by demodulating (multiplying) the V and I using \$V_S\$ (real) and \$V_S\$ phase shifted by \$\pi\over 2\$ (imaginary) and measuring the four resulting voltages after a low-pass filter.

If you were making a bridge specifically for ESR it could be optimized for that purpose- a lower minimum Rs in particular.