Electronic – Unspecified I/O Standard: 5 out of 5 logical ports use I/O standard

vhdl

I keep getting this error when I generate the bitstream in my VHDL code. I'm not sure why its not working, I believe it has something to do with either the constraint file or lower module. My code is similar to my classmates but I'm the only one running into this issue.

here is the full Error message

[DRC NSTD-1] Unspecified I/O Standard: 4 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: a_bL, a_bR, input, and output.

My top module is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab16 is
Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
       led : out STD_LOGIC_VECTOR (7 downto 0);
       btnL : in STD_LOGIC;
       btnR : in STD_LOGIC);
end lab16;

architecture Behavioral of lab16 is

signal A , B , C , D , W , X , Y , Z , bL, bR. c1 : STD_LOGIC;
component Lab16_1
        Port ( a_A, a_bL, a_bR, clock, reset: in STD_LOGIC;
               a_N : out STD_LOGIC);        
    end component;

begin

A <= sw(0);
B <= sw(1);
C <= sw(2);
D <= sw(3);

bR <= btnR;
bL <= btnL;
c1 <= clk;
FlipFlop1:  Lab16_1 port map (a_A => A, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => W);
FlipFlop2:  Lab16_1 port map (a_A => B, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => X);
FlipFlop3:  Lab16_1 port map (a_A => C, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => Y);
FlipFlop4:  Lab16_1 port map (a_A => D, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => Z);
led(0) <= sw(0);
led(1) <= sw(1);
led(2) <= sw(2);
led(3) <= sw(3);
led(4) <= W;
led(5) <= X;
led(6) <= Y;
led(7) <= Z;

end Behavioral;

Lower Module

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Lab16_1 is
    port(
         a_A, a_bL, a_bR, reset, clock : in STD_LOGIC;
         a_N : out STD_LOGIC
        );
end entity Lab16_1;

architecture Behavioral of Lab16_1 is
begin
process (a_bL, a_bR) is
begin
  --if rising_edge(clock) then  
     if (a_bL ='1') then   
        a_N <= '0';
     elsif (a_bR = '1') then
        a_N <= a_A;

     end if;
  --end if;
end process;
end architecture Behavioral;

Constraint File

 ## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]

## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]                    
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]

##Buttons
set_property PACKAGE_PIN W19 [get_ports btnL]                       
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
set_property PACKAGE_PIN T17 [get_ports btnR]                        
set_property IOSTANDARD LVCMOS33 [get_ports btnR]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btnR]

Best Answer

I don't understand how you got it past the synthesis stage, let alone the implementation.

In your top module, you specify component Lab16_1 with a port map that doesn't resemble the actual ports at all.

you write (in the top module):

component Lab16_1
    Port ( input, cl_k, rs_t: in STD_LOGIC;
           output : out STD_LOGIC);        
end component;

whereas your actual ports are declared as

entity Lab16_1 is
port(
  clk : in  std_logic;
  rst : in  std_logic;
  pre : in  std_logic;
  ce  : in  std_logic;
  d   : in  std_logic;
  q   : out std_logic
);
end entity Lab16_1;

Once you've fixed that, you still have the issue that your flip-flop is a latch. I assume you understand this, since you've commented out your usage of the clk signal, but I point it out anyway to make you aware that Vivado will issue heaps of warnings related to this.

Update based on edited post

Your updated code still needs some modification. But if I make the assumption that by:

FlipFlop1:  Lab16_1 port map (a_A => A, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => W);
FlipFlop2:  Lab16_1 port map (a_A => B, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => X);
FlipFlop3:  Lab16_1 port map (a_A => C, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => Y);
FlipFlop4:  Lab16_1 port map (a_A => D, a_bL => bL, a_bR => bR, reset => '0', clock => '1', a_N => Z);

you really mean:

FlipFlop1:  Lab16_1 port map (a_A => A, a_bL => btnL, a_bR => btnR, reset => '0', clock => '1', a_N => W);
FlipFlop2:  Lab16_1 port map (a_A => B, a_bL => btnL, a_bR => btnR, reset => '0', clock => '1', a_N => X);
FlipFlop3:  Lab16_1 port map (a_A => C, a_bL => btnL, a_bR => btnR, reset => '0', clock => '1', a_N => Y);
FlipFlop4:  Lab16_1 port map (a_A => D, a_bL => btnL, a_bR => btnR, reset => '0', clock => '1', a_N => Z);

then, I am able to generate a bitstream. I would suggest you double-check that your project is targeting the right FPGA, and that your constraints file is actually enabled (right-click on the file in the Hierarchy). If you have multiple constraints files, you should also make sure you have the correct one targeted.

One thing which will definitely cause this error message, is if your project does not have lab16 set as your top module. Right-click on lab16 - Behavioral in the Sources⟶Hierarchy tab, and click Set as Top.

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One general method for improving timing is to split logic over multiple cycles by registering results.

You could try something like this...

signal_gen: process (reset, clock25M) begin
    if(reset = '0') then
        counter_15    <= (others => '0');
        counter       <= (others => '0');
        phi1_sig      <= '1';
        phi2_sig      <= '0';
        reset_int     <= '1';
        counter_15_not_done <= true;
        count_lt_000010000000000 <= false;
        count_lt_011100000000000 <= false;
        count_lt_100010000000000 <= false;
        count_lt_111100000000000 <= false;
        count_lt_111111111111111 <= false;
        count_eq_111111111111111 <= false;
    elsif(clock25M = '1' and clock25M'EVENT) then
          --the comparisons are computed in parallel and registered
          counter_15_not_done <= counter_15 < "1111";
          count_lt_000010000000000 <= count < "000010000000000";
          count_lt_011100000000000 <= count < "011100000000000";
          count_lt_100010000000000 <= count < "100010000000000";
          count_lt_111100000000000 <= count < "111100000000000";
          count_lt_111111111111111 <= count < "111111111111111";
          count_eq_111111111111111 <= count = "111111111111111";
          --the logic now only depends on the registered results.
          --The registered results are only 7 bits rather than 19 bits
          --this should have much better timing
          if(count_lt_000010000000000 and counter_15_not_done) then
              phi1_sig      <= '0';
              phi2_sig      <= '0';
              counter       <= counter + 1;
              reset_int     <= '0';
          elsif (count_lt_011100000000000 and counter_15_not_done) then
              phi1_sig      <= '1';
              phi2_sig      <= '0';
              counter       <= counter + 1;
              reset_int     <= '0';
          elsif (count_lt_100010000000000 and counter_15_not_done) then
              phi1_sig      <= '0';
              phi2_sig      <= '0';
              counter       <= counter + 1;
              reset_int     <= '0';
          elsif (count_lt_111100000000000 and counter_15_not_done) then
              phi1_sig      <= '0';
              phi2_sig      <= '1';
              counter       <= counter + 1;
              reset_int     <= '0';
          elsif (count_lt_111111111111111 and counter_15_not_done) then
              phi1_sig      <= '0';
              phi2_sig      <= '0';
              counter       <= counter + 1;
              reset_int     <= '0';
          elsif (count_eq_111111111111111 and counter_15_not_done) then
              counter_15    <= counter_15 + 1;
              counter       <= counter + 1;
              reset_int     <= '0';
          else 
              phi1_sig      <= phi1_sig;
              phi2_sig      <= phi2_sig;
              reset_int     <= '0';
          end if;

        end if;
    end process;
end architecture;

Note that the registered results will lag the actual counts by 1 clock cycle so you may need to adjust the comparison points back 1 cycle.

Best Answer

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