I'm going to start with conclusions and then follow up with some reasoning. Hopefully will be helpful.
- 6.4V will be really marginal \$V_{\text{GS}}\$ for this FET (IRF1405Z). Since the Miller Plateau (Fig 6) occurs at about that voltage, it may not switch fully at these currents. If you can't get about 10V to drive the FET, then you should find a low \$V_{\text{th}}\$ FET to use instead.
- A direct coupled gate drive should be used instead of and AC coupled drive. The application doesn't seem to need an AC drive. And an AC drive will result in lower \$V_{\text{GS}}\$ than even 6.4V.
- There is a big difference between values needed for passive pull down \$R_{\text{GS}}\$ during the slow system start-up dV/dt, and total gate circuit resistance \$R_g\$ for switching operation. \$R_{\text{GS}}\$ can be very high value, like 10KOhms to 100KOhms for the slow (usually milli-sec) start up dV/dt. Total gate resistance \$R_g\$ will typically need to be less than ~200 Ohms for high dV/dt switching. For more about this you should look at this answer which I think explains it all (Yes, I'm biased).
- Because of the voltages involved in this case, only 6.4V, dV/dt isn't really an issue here. If there is really only 6.4V \$V_{\text{ds}}\$, then it won't be possible for dV/dt to drive \$V_{\text{gs}}\$ up to \$V_{\text{th}}\$ of the IRF1405Z.
AC Coupled Gate Drives -- What are they good for?
The only reason to use a capacitively coupled gate drive is if for some reason a negative voltage is needed on the FET gate when the FET is turned off. A problem with the AC drive is that an amount of positive gate voltage is always lost from the input drive levels, and it will be a variable amount depending on the duty cycle of the drive waveform or the clamping voltage.
In this case where the clamp circuit has been removed the peak \$V_{\text{GS}}\$ is a function of duty cycle (DC) as well as source value. The drive signal on the FET side of the coupling capacitor (\$C_c\$) will be normalized to the average value by the passive pull down \$R_{\text{GS}}\$ and would be equal to \$\text{(1-DC)} V_{\text{DRV}}\$. For example with 6.4V \$V_{\text{DRV}}\$, if the switch duty cycle is 50% then the high state \$V_{\text{GS}}\$ would be 3.2V. If duty cycle were 20% the high state \$V_{\text{GS}}\$ would be 5.1V.
Looking at Figure 1 of the IRF1405Z datasheet, \$V_{\text{GS}}\$ of 5.1V results in max drain current of 40 Amps, or not fully on. This would cause the FETs to over dissipate and burn out. With the high currents that will be switched, you can't afford to have low gate voltages for any reason.
dV/dt
The IRF1405Z has 12nH of package inductance in the drain and source connections, and a \$C_{\text{oss}}\$ of ~1000pF at 12V \$V_{\text{ds}}\$. That should limit the \$V_{\text{ds}}\$ rise time for the die to about 10 nsec. Figuring a high Q resonant response for the LC and steady state off voltage for \$V_{\text{ds}}\$ of 6.4V, \$V_{\text{ds}}\$ at the die could ring to 12.8V. That's a dV/dt of about 1V/nsec. Using the equation, from the answer cited earlier, for \$V_{\text{gs}}\$ under dV/dt:
\$V_{\text{gs}}\$ = \$C_{\text{gd}} V_{\text{dsSlp}} R_g \left(1-e^{-\frac{t}{R_g \left(C_{\text{gd}}+C_{\text{gs}}\right)}}\right)\$
And putting in values for IRF1405Z:
\$V_{\text{gs}}\$ = \$\text{(500pF)} \text{(12V/10nsec)} \text{Rg } \left(1-e^{-\frac{\text{10 nsec}}{\text{(500pF + 4500pF)} \text{Rg}}}\right)\$
It is possible to see that any value for \$R_g\$ is going to leave \$V_{\text{gs}}\$ less than about 1V. So, it looks like dV/dt isn't going to be an issue. (Never thought I'd say that!)
You can, but you wouldn't want to connect the bases together like that.
If you're just passing a binary signal, as implied by your LED drive circuit, just leave the bases open as usual.
If you're interested in analog signals, then you would connect the bases to a suitable bias network that establishes a quiescent operating point for the transistors.
But there's rarely a good reason to use two optoisolators when a single one followed by a suitable buffer/driver would do the job.
Best Answer
First, what you show isn't really totem pole but bi-directional emitter follower.
Your basic concept makes sense in that the emitter followers will have current gain equal to the gain of the transistors. However, a problem is that each bi-directional emitter follower stage will lose two junction drops of voltage swing.
Using a single emitter follower stage to drive a FET gate can be appropriate, and I have done exactly that in production designs. However, you have to make sure the FET is still driven to the necessary min/max voltage for good switching. When you're only starting with logic level voltages, losing one junction drop on each side could be a challenge. Losing 4 junction drops due to two cascaded stages most likely won't work. Even with a 5 V logic signal, you'd be left with only around 2.2 V swing on the FET gate.
However, I don't see the point to two current gain stages. You can easily find transistors with a minimum guaranteed gain of 50 for your current and voltages. Actually 100 shouldn't be hard to find with minimal searching. Given that kind of gain available in a single stage, you shouldn't need two stages. 8 mA from your logic gate turns into 800 mA at the FET gate. If you need more than that, you should be using FET driver chips that are intended just for that purpose.
You should also ask yourself whether the logic gate by itself is enough. The gate will be driven a bit slower due to the limited current to charge or discharge the gate capacitance, but does that really matter in your design? I've done lots of designs with microcontroller pins directly driving "logic level" low side N channel switches. If you're only switching a solenoid with 24 kHz PWM, for example, you probably don't need any current gain at all.