Electronic – Using too many Modules in Verilog affect timing

Xilinx UCF is a constraints file format. It is used to apply various constraints on the design to the Xilinx tools, including but not limited to pin locations, timing, and area. When mapping your RTL (VHDL) design to a physical device, you will minimally need clocks and pin constraints at the top level, but constraints for real designs can go much further than this. Xilinx has a User Constraints Guide on this subject.

You can use the system clock if it meets your needs. Very often, real designs require clocks at a specific (lower) frequency, or multiple clocks at different frequencies, which is where clock dividers would be used.

A gentle dead tree introduction to VHDL programming for Xilinx I can recommend is this book. I recommended a book, since I have not found online HDL tutorials nearly as concise or complete as those for software. You should also scour Xilinx's online documentation for their tools and the part(s) you're using.

The problem I see is you have declared count_max as a 1 bit wide wire and then assign a 32bit constant to it - this will essentially get truncated to 1 bit.

This will then mean you are doing additions and comparisons between 32 bit and 1 bit values on line 29, thus you get the issue of it saying truncated 32bit down to 1bit.

Then by extension your calculations optimise away to a single 1bit value (essentially it boils down to if >0, set to 0, else add 1) which will only ever be 0 or 1 and hence why your count[31:1] (notice not the LSB, bit 0) are unchanged in the always construct - because you assign them to always 0.

Also declaring count_next specifically would help - you assign to a non-existent wire, so it creates one for you. In some tools e.g. modelsim, this would be an error, in others at least a warning. The simplest way to do it would be to replace assign count_next with wire [31:0] count_next.

Finally as Brian points out quite rightly in the comments, your conditional is wrong. You use count_next as part of it's own assign statement which is plain bad. It is fine to do that with clocked registers, as there is no risk of creating a design which would oscillate at very high frequencies potentially causing damage to the FPGA. I believe what you meant is (count >= count_max). Notice I also changed to be >=, this is because your count includes zero - say count_max = 5, you would want your counter to go 0,1,2,3,4,0 - notice how there are 5 clock cycles taken to count from 0 to 4 and then go back to 0?