I'm a verilog Beginner.
I created a design using straight-up Verilog then tested it using the ISE design tools. Works great.
I would like to synthesize this to see the resources that will be consumed but to do so seems to require a schematic file. So I created a symbol for the Verilog cicruit and then created a new schematic, plopping my symbol onto the schematic and attaching some I/O markers.
When I tried to compile the schematic (AKA 'Implement the Design'), I got errors on every I/O. Here's an example:
ERROR:HDLCompilers:91 – "mm.vf" line 35 Module 'method2_MUSER_mm' does
not have a port named 'LL1'
The other errors are identical except the line number and port name changes.
My Verilog symbol is indeed called 'method2'. The schematic has a I/O definition for LL1. mm.vf is a file being generated by ISE.
I have no idea what it is looking for or how to fix it.
Best Answer
It sounds like your module symbol probably doesn't have the same name as the underlying Verilog.
Make sure there is a port named LL1 in your Verilog module.