Electronic – Verilog – A line stays high, I need it to go low after a while

programmable-logicverilogxilinx

I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine.

I generate a stepper pulse every X spindle pulses. No problem, works great.

While simulating, however, I noticed that if the stepper signal is high when the spindle pulses stop (say, someone turns off the machine), the stepper signal stays high. This is because I set it back to low on the leading edge of the spindle pulse, and there are no more.

This means that (with a poor implementation) the stepper could be run at full speed which would cause a machine crash. Now, I would hope the stepper controller would operate only on the leading edge, but you never know.

Finally, the question – since I can't depend upon my 'clock' (the spindle pulses) to continue ad infinitum, what's a good way to make the stepper pulse go low after 'a while.'

As you see, I can't even describe it properly so I can't Google it, lol. If someone could supply me with some words to search on (or better yet, describe a standard technique) I'll be off to the races.

Thanks!

EDIT –

I'm experimenting with the following (typed from memory…) Is this sadness, or a good idea?

always @(posedge Stepper) begin
     #50 // or whatever, this is a low Hz system...
     Stepper = 0;
     end

Or does the delay only work in the simulator?

Best Answer

The best way (depending on how complex your final design will be) would probably be to use a separate fast CMOS oscillator for your CPLD system clock, and have it process the input pulses and output the stepper pulse.
This way, the clock is running all the time when the system is on, and it can time the period from the last input pulse - if it's above a certain limit, set the stepper line low.

This is the way a typical synchronous design works, you have an independent system wide clock and this is used to "read" (i.e. into a register) and process external asynchronous signals (as opposed to the external signals clocking the logic directly)

Another simpler way would be to have another input "reset" line that sets all the registers and outputs to a certain state when it goes low. You could then use a simple RC low pass filter on the input pulses so when they stop, the line drops low and the CPLD resets.

Related Solutions

Electronic – How will this Verilog line be synthesized

I'll assume you're working in an FPGA. If you're talking about an ASIC, wait for an answer from someone who knows something about ASICs.

First, is data a wire or a reg, and is it connected to a pin? If it's a wire, the line should begin with the word "assign". If it's a reg, the line should be included in some kind of always or initial or similar type of block. It would also be better to use '<=' in place of '=' to get simulation to better match synthesis.

If data is an inout pin, this will synthesize as a tristate buffer.

If data is an internal register, this is probably not synthesizable code, unless you are working in a very old FPGA (XC4000 era or earlier?). What is actually produced is at the whim of your synthesis tool and might be different for different tools. It would be much preferrable to set to all 0's or all 1's, and then explicitly OR or AND together all the different drivers for the data bus.

In either case, if you are simulating this code, rather than synthesizing it, and there are no other drivers for data, the simulator is quite right to set the value to 'x', because there's no way to predict which way the tri-stated signal will drift in actual use.

Most simulators simply simulate the code exactly as it is, rather than guess what it will synthesize to and then simulate that. That means that un-synthesizable code will simulate perfectly well, even though they won't necessarily behave correctly when implemented in your FPGA.

Electronic – CPLD best practice for resetting a counter

It sounds like you don't have an external reset signal to respond to, you just want to count to some number then go to zero as the next step. You could consider this a mod n counter, where n is one more than the maximum count in your counter.

So I'm not sure what you mean about "losing a signal" while doing the reset. If you had a 3-digit decimal counter and it rolled over from 999 to 000, you wouldn't consider it as "losing a signal", it would just be counting to the next value in mod-1000 arithmetic.

So if you do

always @(posedge clock) begin
    if (counter == some_number) begin
         counter <= 0;
    end
    else begin
        counter <= counter + 1;
    end
end

You'll have a counter that counts continuously in mod-some_number+1 arithmetic. Alternately you could say it counts to some_number, then resets to zero without ever "losing" a clock pulse.

If some_number+1 happens to be a power of 2, you don't even need the reset condition in your code. For example, for a mod-16 counter, you can just use a 4-bit counter, and the synthesized logic will count continuously and repeatedly from 0 to 15.

Best Answer

Related Solutions

Electronic – How will this Verilog line be synthesized

Electronic – CPLD best practice for resetting a counter

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