Electronic – VHDL debouncer circuit

debouncevhdlxilinx

I'm working in a digital engineering lab and I'm trying to figure out how this debouncing circuit works. It's provided as-is by Xilinx but I'm not quite sure why it does what it does. Any pointers, perhaps? Following is the VHDL code:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity Debouncer is 
    Port ( CLK : in  STD_LOGIC; 

           Sig : in  STD_LOGIC; 
           Deb_Sig : out  STD_LOGIC); 
end Debouncer; 
architecture Behavioral of Debouncer is 
 signal Q0, Q1, Q2 : STD_LOGIC := '0'; 

begin 
process (CLK) is 
begin 
 if (CLK'event and CLK = '1') then  
  Q0 <= Sig; 

  Q1 <= Q0; 

  Q2 <= Q1; 

 end if; 

end process; 

Deb_Sig <= Q0 and Q1 and (not Q2);

end Behavioral;

Best Answer

I'm not familiar with VHDL, but it seems to be doing this: output Deb_Sig is 1 only when input Sig has been 0->1->1 (time grows to the right), sampled at the rising edges of CLK. Otherwise, Deb_Sig is 0. So, the module detects rising edges at the input, and only those ones that are followed by a high level that, after sampling, turns into at least two logic 1 samples. That way, it will ignore pulses that are high during only one sampling instant, which will be considered noise.

I would say that your code synthesizes something equivalent to this:

Curiously enough, it may ignore high pulses that last 2T-epsilon (where T is the sampling period), and detect high pulses that last T+epsilon (which is shorter than 2T-epsilon), if the sampling is such that it sees only one logic 1 in the former pulse, but two logic 1s in the latter one.

Related Solutions

Electronic – Why is the simple counter VHDL not working? Where did the signals go

the rising_edge() parameter is only really for clock signals. One option would be the following:

clk_proc: process( clk, switch1, switch0 )
begin
    if switch1 = '1' then
        counter <= ( others => '0' );
    elseif rising_edge( clk ) then
        if switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

clk_proc: process( clk, switch1, switch0 )
begin
    if rising_edge( clk ) then
        if switch1 = '1' then
            counter <= ( others => '0' );
        elsif switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a lot easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.

Electronic – Problem in synthesizing

Inside ringcounter, q3 is being assigned by both the concurrent assignment q3<='1' and DFF4. You can't have both at the same time.

Best Answer

Related Solutions

Electronic – Why is the simple counter VHDL not working? Where did the signals go

Electronic – Problem in synthesizing

Related Topic