Electronic – VHDL Delimiter Character

fpgaspartanvhdl

I'm trying to define a string in VHDL with a pair of double quotes in the string itself. However I am unable to do so because the IDE (Xilinx ISE 14.7) only recognizes what's in-between the first pair of double quotes as the string. Is there some kind of delimiter or escape character I can use?

Here's the string definition:

constant AT_WKMOD       : string(1 to 15):="AT+WKMOD="SMS""&CR;

If I try:

constant AT_WKMOD       : string(1 to 15):="AT+WKMOD=/"SMS/""&CR;

It does the same thing. The last thing I tried was:

constant AT_WKMOD       : string(1 to 15):="AT+WKMOD=\"SMS\""&CR;

Which gives the following error upon synthesis:

Non-printing character is not allowed in extended identifier.

Best Answer

Since answers should be written as answers and not comments, I'll summarize here:

IEEE Std 1076-2008, section 15.7 - String literals

A string literal has a value that is a sequence of character values corresponding to the graphic characters of the string literal apart from the quotation mark itself. If a quotation mark value is to be represented in the sequence of character values, then a pair of adjacent quotation marks shall be written at the corresponding place within the string literal. ... The length of a string literal is the number of character values in the sequence represented."

For example:

constant AT_WKMOD: string (1 to 15) := "AT+WKMOD=""SMS""" & CR;

As an alternative, you can always create a string by concatenation, "AT+WKMOD=" & '"' & "SMS" & '"' & CR; as you are already doing with CR. Note '"' is a character literal, i.e. a " enclosed in a pair of 's.

Related Solutions

Electronic – use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E

No. Only the vendor's tools produce .bit. But you can use many for simulation. You may just need a Xilinx library for it.

Electronic – Writing a VHDL Module

I'm pretty sure you accidentally clicked "Verilog Module" instead of "VHDL Module":

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The code generated should look something like this:

   COMPONENT mymodule
   PORT(
      clk    : IN std_logic_vector(3 downto 0);
      enable : IN std_logic_vector(3 downto 0);   
      output : OUT std_logic_vector(3 downto 0)
   );
   END COMPONENT;

Delete the accidental Verilog Module and try again paying close attention to which Source Type you choose.

Best Answer

Related Solutions

Electronic – use ghdl or some other VHDL compiler/simulator than WebPack with a Spartan 3E

Electronic – Writing a VHDL Module

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