Electronic – VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to ‘0’

fpgaprogrammable-logicvhdlvivado

I'm attempting to create synthesisable VHDL that will demultiplex a one-bit continuous signal stream to one of many outputs. The outputs that aren't being sent this stream should be set to '0'. See image below for an idea of what I'm trying to achieve.

The code I've written to create this functionality is:

send_s         <= (line_select_s => prbs_i(0), others => '0');

where 'prbs_i(0)' is the signal stream.

Unfortunately this is unsynthesisable in Vivado, giving the error:

[Synth 8-211] could not evaluate expression: aggregate choice expression

Is there a proper way to do this? The VHDL simulates fine but will not synthesise.

Best Answer

The problem with your code is that an assignment of the form:

a <= (3 => '0', others => '1');

must use constants for the offsets being assigned (in this case, 3).

If you need the offset being set to vary, you have to split it into two assignments. Note that this will only work inside a process; with a pair of concurrent assignments, you would encounter a multiple driver problem.

process (line_select_s, prbs_i)
begin
  send_s <= (others => '0');
  send_s(line_select_s) <= prbs_i(0);
end process;

This works because although we start by assigning '0' to the whole vector, the last assignment to a particular signal in a process will take priority.

An alternative is to use a loop:

process (line_select_s, prbs_i)
begin
  send_s <= (others => '0');
  for i in send_s'range loop
    if (i = line_select_s) then
      send_s(i) <= prbs_i(0);
    end if;
  end loop;
end process;

This has the advantage that if your select signal can represent an offset larger than the width of your target vector, no error will be produced in simulation. An example scenario would be a 3-bit select signal, but a target vector with only 5 elements; the first method would produce an error if the select signal represented 6, 7, or 8, but the second would not.

As a side note, you may want to make a process like this synchronous if you want to get the best performance (in terms of maximum operating frequency) out of your design.

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VHDL – Troubleshooting Wrong Outputs in VHDL Entity

The first thing I see, which isn't likely causing your problem, is a lack of any kind of reset. ModelSim does not automatically declare all signals to be '0', and trying to say s <= not s when s is not 1 or 0 is not going to give you what you want. I see you declaring them all '0' at the top but a proper circuit would have a reset input that you briefly drive at the start of your simulation.

Your basic counter process looks wrong; basically when the count reaches ten you're outputting a '1' and for the other 9/10ths of the time you're outputting a '0' (for the 100k example, the 1Hz example would be a 1us pulse high and a 999us low time. I think what you want is something like this:

gen_clk100: process(clk, rst)
begin
    if rising_edge(clk) then
        if count = 10 then
            clk100 <= not clk100;
            count <= 0;
        else
            count <= count + 1;
        end if;
    end if;

    if rst = '1' then
        clk100 <= '0';
        count <= 0;
    end if;
end process;

Note several things:

I'm not incrementing all the time. I increment if the count is not at its max, and increment otherwise.
I'm toggling the output clock when the maximum count is reached
I've included an asynchronous reset (with synchronous clear) -- this ensures that your signals initialize correctly and have no metastability problems when reset is released.

You also mention that the other sections are the same. I think you're having a problem with multiple drivers like Yann mentioned. Check and double-check your code to make sure you are not assigning the output in two different processes, because that is exactly what the simulation is saying you're doing. Better to either make a generic counter module or...

Why so many counters? All your frequency dividers can be handled with a single count and then "peeling off" the conditions to do the divisions you're interested in. You could also have a single counter and use the mod (modulus) operator to handle each divider case.

Finally, I'd also use real or integer types for the count instead of std_logic_vectors but that's just me.

LFSR Using D Flip Flops

I think the things that is really missing from your design are signals, signals exist inside the architecture and can be assigned in much the same way as a port but without an interface to the outside world, a signal can be written to and read from and can be any type you like and an output can be assigned a signal of the same type so for your design consider using an internal register and then assigning it to your output.

Here's an example of what I mean:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_std.all;

entity lfsr is

    port (

        -- Clocks
        clkin                                   :in  STD_LOGIC; 

        -- Initialisation data
        first_key                               :in  STD_LOGIC_VECTOR(3 downto 0);

        -- Control Signals
        key_set                                 :in  STD_LOGIC;
        push                                    :in  STD_LOGIC;

        -- Outputs
        data_out                                :out STD_LOGIC_VECTOR(3 downto 0);              
        );

end lfsr;   

architecture RTL1 of lfsr is    

    signal key                      :STD_LOGIC_VECTOR(3 downto 0);

begin                                                                                                               

    -- Generate a key every time the push signal is asserted
    process(clkin)
    begin

        if rising_edge(clkin) then

            if key_set = '1' then -- Initialises the key

                key <=  first_key; 

            elsif push = '1' then -- Generate a new key

                key(2 downto 0) <=  key(3 downto 1);
                key(3)          <=  key(1) XOR key(0);

            end if;

        end if;

    end process;

    -- Send internal key to output port
    data_out    <=  key;

end RTL1;

so the signal that I have created is key, it is internal to the architecture and what it actually represents is a block of memory 4 bits wide. This code actually does what you want, it is a LFSR that will generate pseudo random data but I have made it 4 bits wide instead of 8 because I didn't want to just give you the answer and if you can understand what this code does, you will be able to understand how to expand it to 8-bits and it will be a great start to understanding VHDL.

If you have any questions about my code then please ask,

Gipsy

Best Answer

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LFSR Using D Flip Flops

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