Electronic – VHDL Flip Flop Syntax Error

flipflopsynthesisvhdl

I'm trying to figure out how to VHDL, and am having some difficulties writing a simple flip flop. I want a T flip flop that runs strictly off of the clock, changing state every time it receives a rising edge.

The syntax errors are somewhat cryptic and I'm having difficulty figuring out what is wrong.

library lattice;
use lattice.components.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity blinker is
    port(
            clk     :   IN  STD_LOGIC;
            ledout  :   OUT STD_LOGIC
    );
end blinker;

architecture Behavioral of blinker is
    signal ledState: STD_LOGIC;
begin
    process(clk)
    begin
        if(rising_edge(clk)) then
        --if clk'event and clk='1' then
            if ledState = '1' then
                ledout <= '0';
            elsif ledState = '0' then
                ledout <= '1';
            endif;
        endif;
    end process;

    ledout <= led_state;

end Behavioral;

I attempted two methods of running on a rising edge, neither seemed to make a difference. This is what the output looks like:

enter image description here

I'm completely lost at this point. What am I doing wrong here?

Thanks!

Best Answer

You have a few issues:

1. endif; should be end if;

2. You already have assignments to ledout within your process, but then you attempt to assign a value to it again in the last line ledout <= led_state;. You can't have multiple drivers for a given signal.

3. Your code is a little over-complicated. You can simplify the toggle of signal ledState like so: ledState <= not ledState; without the embedded if/elsif clause.

4. One of the error messages is pointing out a typo you made in the last line ledout <= led_state;, where I think you meant ledout <= ledState;

Try this instead:

library ieee;
use ieee.std_logic_1164.all;

entity blinker is
    port(
            clk     :   IN  std_logic;
            ledout  :   OUT std_logic
    );
end blinker;

architecture Behavioral of blinker is
    signal ledState: std_logic := '0';
begin
    process(clk)
    begin
        if(rising_edge(clk)) then
            ledState <= not ledState;
        end if;
    end process;

    ledout <= ledState;

end Behavioral;

RTL RTL

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