Electronic – VHDL how to make a process with sensitivity list wait

vhdl

I'd like a process to listen to changes in a signal, but not before 20 ns. How can I achieve that?
It doesn't seem possible to use wait statements in such a process, which makes sense since is has a sensitivity list.
What I'm really trying to achieve is a test bench that changes one signal indefinitely and another for like 5 ns after signal ready = '1'. But I don't know precisely when that will happen. I only know that before 20 ns the system is still resetting and hence I should not listen to changes in ready before 20 ns because then I'd get errors.
Alternatives to the approach in the question are welcome.

Best Answer

For much testbench code, we do not use looping processes and process sensitivity lists to search for things. Instead, we use wait to find events.

TestProc : process 
begin
  Out1 <= '1' ; -- Steady 1 after this point.

  -- Find Reset as it deactivates
  -- a better alternative than waiting for an ad-hoc amount of time
  if Reset /= ACTIVE then
    wait until Reset = ACTIVE ; 
  end if; 
  wait until Reset /= ACTIVE ; 

  -- find ready at a level 1
  if ready /= '1' then 
    wait until ready = '1' ; 
  end if ; 
  Out2 <= '1' after 5 ns ; 

  -- find a rising edge of Clock
  -- Assumes that clock always transitions from 0 to 1 
  wait until Clk = '1' ; 
  Out2 <= '0' after 5 ns ; 
  ...

  -- Also find a rising edge of Clock
  -- rising_edge is extra work for the simulator and probably not necessary here
  wait until rising_edge(Clk) ; 
  Out2 <= '1' after 5 ns ; 
  ...

  std.env.stop ; -- stop the testbench
end process TestProc ;

If you are looking for a behavioral model that drives Out1 to a static value, but inverts Out2 5 ns after each time Ready rises to a 1, then you can do the following:

signal Out2 : std_logic := '0' ; 
. . . 
FollowReady : process  
begin 
  -- initialization 
  Out1 <= '1' ; 
  wait for 20 ns ; 

  -- looping process like behavior
  loop 
    -- Ready is a design signal.  Only detect a 0 to 1 change
    wait until rising_edge(Ready) ;
    Out2 <= not Out2 after 5 ns ; 
  end loop ; 
end process ;

Related Solutions

Electronic – VHDL: when is process sensitivity list triggered

Time is only advanced when no more processes can be awakened by any event. If process "P" is awakened by its sensitivity list, it will execute in zero time and schedule signal assignments, and these assignments may awaken other processes. If at the next delta (which does not advance time) any process (including itself) affects P's sensitivity list, then P will be re-awakened. This happens as many times as necessary (or until the simulator gives up or the set maximum number of deltas have occurred).

In the particular example of your question with ABC = 101, if you had:

process(A,B) begin 
    B <= not A; 
    C <= A xor B;
end process;

process(C) begin
end process;

When A changes to 0, BC are scheduled with assignments of 10. A delta passes, B becomes 1 and re-awakens the process, which schedules C back to 1. At the end of this second delta the values are 011, and there are no more events that could awaken the process, and when no other process can be awakened, time advances.

Consequently, process(A,B) is awakened once when A changes, and a second time when B is changed. As a result, the "process awakening counter" counts twice.

In the case of process(C), it will also be awakened twice, because C will "delta glitch" due to process(A,B).

However, if B was implicit:

process(A) begin 
    C <= A xor (not A);
end process;

process(C) begin
end process;

Or if B was a local variable:

process(A) 
    variable B : std_logic_vector;
begin 
    B := not A;
    C <= A xor (not B);
end process;

process(C) begin
end process;

Then process(A) would only be awakened once, but process(C) would remain suspended.

Electronic – difference between sensitivity list and wait vhdl

The two processes as you have written them are almost equivalent. If you move the wait statement to the end of the second process, then they are exactly equivalent. The difference is whether or not the body of the process gets executed before the first change on any of the listed signals.

IEEE Std 1076-2008 11.3 para 4 (in part):

If a process sensitivity list appears following the reserved word process, then the process statement is assumed to contain an implicit wait statement as the last statement of the process statement part; this implicit wait statement is of the form wait on sensitivity_list ; where the sensitivity list is determined in one of two ways. If the process sensitivity list is specified as a sensitivity list, then the sensitivity list of the wait statement is that following the reserved word process. ...

Best Answer

Related Solutions

Electronic – VHDL: when is process sensitivity list triggered

Electronic – difference between sensitivity list and wait vhdl

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