Is it ok to use an "ordinary" via to connect the Exposed Pad of an TQNF package to ground, as shown in the following picture?
I am using eagle. DRC generates an "overlap" error, is it ok to ignore this error?
Can this design cause board assembly issues (I'm planning to do machine assembly)?
Best Answer
Vias will not impact the assembly of the PCB provided that their effect is carefully considered in the assembly process.
Many RF ICs and SMD power MOS devices require solid thermal connections to internal planes in order to wick away generated heat and endure a low impedance GND path. Vias are known to wick up solder paste during the reflow process and there are several options to mitigate this. The correct combination of via count, via size and solder paste mask will ensure a very repeatable assembly process.
The screen capture above is of a GPIO expander with 16 non-plugged vias which are tented only on the bottom side. It is a 6 layer board with solid 1oz ground planing on all layers. Paste mask is revealed in grey. Most IC manufacturers will specify the solder paste and via requirements, otherwise it may be extracted from IPC-7351-2004 Generic Requirements for Surface Mount Design and Land patterns. There are also many free and open source land pattern generators online.