cpuintegrated-circuitmemoryram
Okay so I know when I need to build a parallel design I can put them near each other and make a 4k*8 to expand the databus. But on this one I only need to use half of them and the databus length is larger than my total chips can reach. But I thought 2k*12 requires 24k b of data and i have 32k of space to store data. So there has to be a way to do so.
When I use a parallel design I can reach 4k*8 but it is not enough.
The 74HC244 is the typical device for connecting to/disconnecting from a bus. It's an octal tri-state buffer (or rather a dual quad buffer). You'll need the tri-state feature to disconnect completely from the bus. The gates would set the bus high or low, but that wouldn't allow another device on it.
But since you're talking about a data bus you probably want a bidirectional buffer. Then you can use the 74HC245.
You have a DIR pin to control the direction and a /OE which can make the buffer tri-state.
edit
JustJeff mentions the 74HC374 octal tri-state D flip-flop. (Note: I'll talk about the 74HC574, which is functionally the same, but has a more logical pinout.) The 74HC574 is indeed an interesting part, and a classic since the SN74xx series. While the 74HC245 will give you a tri-state buffer, the 74HC574 has a memory function too, in the form of an octal D flip-flop. Great to make registers, and through the tri-state connection to the bus you can route your data flow easily.
There's a drawback to this, however. The register's output is only available to the bus, so all communication would have to pass there, so that the bus will become a bottle-neck. Therefore I think it's better to replace the 74HC374 by a 74HC273 octal D flip-flop followed by a separate 74HC244 tri-state buffer for the connection to the bus. That way the register's output is also available internally when some other signal occupies the bus. (I don't know if there's a function compatible part with the more logical pinout. You may also use a 74HC574 with /OE hardwired to ground.)
It's not clear what you are really asking, but it is common to store binary values that are wider than the addressable unit of memory. For example, if you want to store 16 bit words in a byte-addressed memory, then you use two bytes. That also means the software has to know which byte is stored first.
In your case you seem to have native 4 bit words. To store a 16 bit value, use 4 words. Again, your software will have to know what convention you are using, like low word first or high word first.
Since your memory only has 4 address lines, its size is limited to 16 native words. Your native word size appears to be 4 bits, so your memory can hold only 64 bits. That means it will be completely used up by two 32 bit values or four 16 bit values, for example.
Best Answer
The only way to increase the apparent width of a physical memory is to wrap it in a sequential circuit that executes multiple cycles internally for each external read or write cycle. This requires a means of multiplexing the data during write cycles and demultiplexing it during read cycles.
For example, you could turn your 4k × 8 physical memory into a 2k × 16 virtual memory by storing each 16-bit word in two consecutive 8-bit locations in the physical memory. The physical memory would execute two read or write cycles internally for each external cycle.