Electronic – weird Altera simulation result

You have unfortuantely run into a relatively subtle problem with this particular flip-flop. (BTW, this is not metastability; that's a different problem.) It's designed to operate at high speed over a wide range of supply voltages, and one of the compromises made in its design is that it has a rather strict requirement on the clock input transition speed.

If you look at section 9 of the datasheet, the input transition rate is given as 10 ns/V maximum. This means that you need to make the clock rise or fall by 5 volts in no more than 50 ns in order for the chip to operate correctly. With an RC time constant of 10 ms, you are about 6 orders of magnitude too slow.

I'd guess 2 possibilities. The first (and one you should be dealing with anyways) is that you don't have a decoupling capacitor on your flip-flop. You need a 0.1 uF ceramic between V+ and ground, as close to the chip as you can get. Putting it on the breakout board is best, assuming you can without damaging the chip.

The second possibility has to do with your connection to the signal generator. How long is the wire, and how fast are the transitions? If you're not properly terminated and the leads are long, the flip-flop may be responding to ringing on the clock line.

Your connection does not require worrying about timing from input to output. A delay will not make a difference.

Neither of your chips are differential, so I really can't advise you on this issue.

You are handling set and reset lines exactly right.

And while it's a little late, you might consider a different flip-flop. Since you're working with protoboards and are clearly new to the subject, I'd suggest that you get a few 74HC74s in DIP packages. These will simply plug into your protoboard without the need for adapters. For learning how logic chips work, this is a whole lot easier on the eyes and pocketbook that trying to start with little surface mount devices.