Electronic – Weird reset problem in FPGA Design

With an FPGA you can make use of the fact that your flipflops will initialise to a known state and create an internal synchronous reset signal which you can "and" with the external one.

When using an external reset, make sure that you synchronise it to the internal clock (with a different synchroniser for each clock if you have more than one) otherwise you may find that your logic comes out of reset in weird ways. This is because the signal will have different delays to different parts of your circuit and if the reset button is released just before a clock edge, some parts of the FPGA will see it (as the reset signal made it to them before the clock signal) and other parts will see it one clock cycle later (as the reset was slightly delayed and therefore missed the clock edge).

You should assume the clock input to your flip-flops is toggling unless you can prove otherwise (by a guaranteed power on or post configuration delay). All the flip-flops on a given clock domain are not guaranteed to start on the same clock edge based on GWE or GSR. Both act like an asynchronous reset and cause potential problems for some logic (counters, one-hot state machines, etc).

Specifically a one-hot state-machine that transitions immediately after configuration WILL (eventually) FAIL (transition to an invalid state). The frequency of failure will depending on the clock period compared to the device (and place and route) specific skew for your design.

Another simple experiment to see this behavior initialize a relatively fast count down counter with 10000000 and look at its behavior immediately after configuration. Some bits make the transition to 01111111 and some bits miss that first transition but the subsequent counting sequence will be correct.

The white paper mentioned by Krunal Desai talks about this very problem and is a great reference. Any SRAM based FPGA will most likely have a similar issue.

There is no need to reset the registers to get a known value. If you have logic that is sensitive to all starting on the same clock edge will need to add synchronization logic (this can consist of a synchronously de-asserted reset or other synchronous logic). Xilinx AR44174 talks about the issue a little more. I would add a third method of mitigation which is to guarantee clocked logic is not changing/transitioning during the first several clock cycles after startup.