# Electronic – What actually happens when both 1 input is given in RS flip flop circuit (physical change)

damagedigital-logicflipflop

This question is somewhat similar to:

Why is S=1, R=1 state forbidden in RS flip flop?

But I am asking what actually happens if both 1 input is given forcefully in R and S terminal of flip flop circuit. Will there be any physical change? Will the flip flop circuit burn or get damaged? What will happen?

In the original question, it is written that:

But if you set both R and S to 1 we have that Q = 0 and \$\bar{Q} = 0\$ at the same time. This contradicts the relation \$Q = \bar{Q}\$.
In the real world one of the gates will reach the 1 state first and
the result will be unpredictable.

This is true theoretically. Both the output will be 0 which is not possible as both the output are complement to each other. So, is it correct to write the truth table of flip flop circuit in the following manner(here):

instead of writing \$Q = \bar{Q} = 0\$ when R = S = 1. This can be written as output cannot be determined as this case is not possible. We cannot say which output will give 0 and which will give 1. This is mentioned here (from the same link):

R = 1 and S = 1: This condition violates the fact that both outputs are complements of each other since each of them tries to go
to 0, which is not stable configuration. It is impossible to predict
which output will go to 1 and which will stay at 0. In normal
operation this condition must be avoided by making sure that 1's are
not applied to both inputs simultaneously, thus making it one of the

It is written that this case must be avoided. What worse would happen if it is not avoided? Will it get damaged or burned?

This is an RS flip flop made from NOR gates

simulate this circuit – Schematic created using CircuitLab

We note that both gates are symmetrical, so there's no need to figure out what both gates are doing.

Each gate is basically an OR function, that generates an output TRUE when either or both inputs are TRUE. If R is '1' or TRUE, then the output will be TRUE. It's an inverted output, so output TRUE is '0'.

So there's your answer. With a NOR-based flip-flop, when both R and S are '1', both 'Q' outputs are '0'. Perfectly predictable.

No problem, unless you insist that the Qs are complements of each other. They are, for at least one of R and S being '0', the normal or expected mode of operation of the flip-flop.

If you make the false assumption that the outputs are always complements of each other, then the R,S='1' state violates that assumption. If you had logic following which basically said if Qa==Qb, then ignite Doomsday Bomb, the consequences could be very serious. But the NOR gates are perfectly happy, doing exactly their logic thang without problems.

Where life does get unpredictable is if we take R and S back to '0' simultaneously after they've both been at '1'. They will 'race' back to a '01' output, the winner getting to '1' first, with the other settling for '0'.

In the ideal case of equal delays, it will be unpredictable which will win. Given the likelyhood of small differences in delay, either in the gates themselves, of the logic driving the R and S inputs, one will tend to always win.

In the unlikely case of very closely balanced delays, the outputs may go metastable, which is both outputs go to a mid-rail voltage, and stay that way for an unpredictably long time, which could exceed their rated propagation delays by a factor of several.