Electronic – Is D flip flop can be combination circuit

Internally, a flip-flop (the term includes everything from simple D latches to more complex edge-triggered J-K master-slave flip-flops) is an asynchronous state machine. It is created by combining ordinary logic gates with feedback.

For example, here's one way to construct a master-slave D flip-flop:

^{simulate this circuit – Schematic created using CircuitLab}

Each of the internal sections is a simple set-reset latch with an enable input. Because the two enables are driven with opposite levels of the "CLK" input, the output can only change state on its rising edge.

Note that while this design is conceptually simple to understand, it is NOT typical of how commercial chips (e.g., 7400-series) are constructed internally. If you study SSI/MSI databooks (the older TI books were especially good), you'll see several other ways to construct flip-flops from gates.

Once you have an edge-triggered flip-flop of any sort, you can use it (or multiple copies of it) to create synchronous state machines that only make transitions on clock edges.

No, your circuit is still a edge-triggered circuit. The pairs NAND1+NAND2 and NAND3+NAND4 lock the state of D when the clock rises from to low to high. Changing D when the clock is high (after the rising edge) does not affect the output.

Let's start with Clk = 0, then is S=1 and R=1.

Now let D=0 during the rising edge of the clock:

• The output of NAND4 will be high.
• The output of NAND3 will be low, because S is still high, thus R=0 => Q=0.
• The output of NAND1 is low.
• The output of NAND2 is high, thus S is high, and R keeps low.

The output of NAND4 will be kept high until the clock is low again because the input connected to R is low regardless of any change on D (after the rising edge).

Please note that the functionality of this circuit relies on the propagation delay of the gates.