Electronic – What are real use cases multiple verilog wire drivers

verilog

Currently, learning Verilog. I found out there are few net types that can have multiple drivers and the value on the net will differ according to the type of net if wire orwand or wor or others.

I grab this, but why on earth anyone would use that ??
What are real life use cases ?

Also I feel like wand and maybe wor are not synthesizeble, am I right ?

Best Answer

It's true that you don't see this type of logic at the RTL level, but there are many technologies that use this at the device level, like open collector circuits, and emitter coupled logic. Also, these devices tend to consume more power, so they are only used where very high speed is required.

Related Solutions

Verilog – Iterating Over All Cases In Testbench

If you treat the inputs as a bus, you can add 1 to them until they overflow. Something like this works (online simulation):

initial begin
  $monitor("%d %d %d %d", A, B, C, D);
  {A,B,C,D} = 4'b0000;
end 
always begin
  #10;
  {A,B,C,D} = {A,B,C,D} + 4'b1;
  if (&{A,B,C,D}) begin
    #10;
    $finish;
  end
end

Connected to Multiple Drivers Problem Verilog

Here, the signal BCD0 is being assigned values under 3 separate 'always' processes. Hence the synthesis is returning multiple driver error. Try moving all assignments of BCD0 signal under a single 'always' process. That will solve the issue. You could use different conditions under the same always block itself to define the behaviour of the signal.

The BCD counter which you are trying to implement is sensitive to clock edges, clear, up as well as down signals. So the process should be sensitive to clock edges and all other signals can be sensed w.r.t clock edges. One way of rewriting the code is like:

always @(posedge Clock) begin  
  if (Clear) begin  
    BCD1 <= 0;  
    BCD0 <= 0;  
  else if (up == 1) begin  
    if (BCD0 == 4'b1001) begin  
        BCD0 <= 0;  
        if (BCD1 == 4'b1001)  
          BCD1 <= 0;  
        else  
          BCD1 <= BCD1 + 1;  
        end  
    else  
        BCD0 <= BCD0 + 1;  
    end  
  else if (down == 1) begin  
    if (BCD0 == 4'b0000) begin  
        BCD0 <= 4'b1001;  
        if (BCD1 == 4'b1001)  
          BCD1 <= 4'b1001;  
        else  
          BCD1 <= BCD1 - 1;  
        end  
    else  
        BCD0 <= BCD0 - 1;  
    end  
  end  
end

Here, all sensitivity conditions of both BCD0 and BCD1 signal are captured under a single 'always' block which will synthesize it properly.

Best Answer

Related Solutions

Verilog – Iterating Over All Cases In Testbench

Connected to Multiple Drivers Problem Verilog

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