Electronic – the difference between an array and a bus in Verilog

fpgaverilogvivado

I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following?

What is the difference between an array and a bus?
- During declaration, a bus would look something like reg [9:0]data while an array would be reg data[9:0]. Is there a subtle (or not-so-subtle) difference in how the language handles these cases?
- Why are is a bus declared with and index in front of the variable name, but referenced with an index behind? For instance, data[3] would work regardless of whether data is declared as an array or bus.
I have found it is possible (although confusing) to create declarations such as reg [4:0]busArray[3:0], which would create 4x 5-bit registers.
- Is this bad practice?
- How is this different from 2d array declared reg arrayArray[4:0][3:0]?
When should I use a bus and when should I use an array?

I have a few other related questions as well…

When you have a declaration like reg [7:0]data[1023:0], is is possible to access individual bits and ranges?
- I have had trouble accessing ranges of bits. For instance, data[7:0][4] seems to work, but data[0][255:0] or data[3:1][512:64] results in a syntax error. Are there rules about how you can access elements in busses and arrays?
Is is possible to declare a multi-dimensional bus? (something like reg [15:0][8:0]data)
Is there a way to type cast an array so that it is treated like a bus? This could be useful in order to pass an array into a module designed to accept a bus.

Best Answer

A bus enables you to define values that are wider than one bit. If you want to store or transmit (in parallel) a value between 0 and 15, you need a 4-bit bus. An array lets you store multiple values under a single name.

The difference between "[7:0] data" and "data[7:0]" is that the first is a single 8-bit-wide value while the second is eight single-bit values.

It's totally normal and useful to create an array of busses. They're sometimes called memories, because you can use them to model ROM or RAM. Your synthesis software can usually recognize when you've defined something that looks like ROM or RAM (for example, reg [7:0] data[1023:0] is basically 1K by 8-bit RAM) and synthesize it as actual physical ROM or RAM on the chip.

To understand which construct to use, just ask yourself what you have. Do you have a single multi-bit value? That's a bus. Do you have a bunch of single-bit values that you want to reference using a single name? Then use an array. Do you have a bunch of multi-bit values? Then use a memory.

Related Solutions

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Electronic – Difference between @* and @(*) in Verilog

There is no difference, they mean exactly the same thing: infer my sensitivity list from the contents of the block.

Best Answer

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Electronic – Verilog asynchronous reads of regs – and design question

Electronic – Difference between @* and @(*) in Verilog

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