Electronic – What are the general steps used in creating a ASIC

asicphysical-design

I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered

  1. Once a logic design is tested on an FPGA it can be ported to an ASIC with relative ease.
  2. The ASIC is created on a Wafer of ~1000 chips
  3. That wafer is chopped up into smaller chips called "dicing"
  4. "bumping"
  5. Packaging: (not sure what this means: "Aligning the substrates to the fiduciary marks")

As you can infer, I'm a little confused and overwhelmed by the process, but I want to get a handle on what is required and what the end to end process looks like.

Where can I find a detailed list of what happens after I test my FPGA logic and am ready to create several thousand ASICs based on that design?

Best Answer

If you say you have a 'design ready on an FPGA', then I'll assume you have some verilog design which you have verified and tested on an FPGA. To get from here to an ASIC, you would go through the following (rough) steps:

Front End Design

  • The 'front end' of the design cycle generally includes writing of the RTL, and the synthesis of that RTL into a gate level netlist. I'll assume you are starting somewhere in the middle of this.
  • Once you have the RTL, you need to run through the synthesis flow, which converts your RTL into a 'gate level netlist'. An example of software used to do this might be DesignCompiler, by Synopsis.

Back End Design

  • The 'back end' of the design cycle refers to converting your gate level netlist into a 'picture' of an ASIC that would be understood by a silicon foundry.
  • First step would be to run initial floorplanning and place and route, which is essentially picking where you want each gate in your design to be positioned in the IC, as well as figuring out how to connect each of these gates in a finite layer of wires.
  • At this point you might run timing checks (see: Synopsis PrimeTime) to make sure that your design meets your required clock frequency.
  • Once you have your design fully specified, then you need more software (ex. Cadence Virtuoso) which can export your design into the file formats understood by a foundry (GDSII, for example).

Fabrication

  • At this point, you have your GDSII in hand, and you call up a contract foundry like TSMC, negotiate with them, and then hand them several million dollars and your GDSII, and wait for 3-6 months. TSMC then takes your design, creates the layer masks, and etches several thousand of your designs into wafers, then slices the wafers up for packaging.
  • The ASICs at that point likely go to a contract assembly, where they will be bumped (solder applied to the pads on the bottom of the silicon for soldering to a package), and then packaged (the bumped chip will be attached to whatever kind of package you require, be that QFP, DIP, BGA, or whatever you need).
  • At this point your IC is packaged and ready to go, and will be shipped back to you.

There's also a lot of testing that goes on between each step here which I've mostly omitted. Also note that each piece of software mentioned here likely costs in the 6 figure range, and there's probably a few more that I neglected to mention.

Also as I mentioned in my comment, here's an informative excel sheet which gives a rough estimate of the costs of each step: http://www.dz.ee.ethz.ch/?id=1592

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