Microcontrollers, FPGAs, ASIC (Application-specific integrated circuit) all are used for similar type of applications (at different levels). I know about microcontrollers and FPGAs. But what is an ASIC really? I have a hard time understanding why we have all off these very similar technologies.
Electronic – What are the practical uses of ASIC
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If you say you have a 'design ready on an FPGA', then I'll assume you have some verilog design which you have verified and tested on an FPGA. To get from here to an ASIC, you would go through the following (rough) steps:
Front End Design
- The 'front end' of the design cycle generally includes writing of the RTL, and the synthesis of that RTL into a gate level netlist. I'll assume you are starting somewhere in the middle of this.
- Once you have the RTL, you need to run through the synthesis flow, which converts your RTL into a 'gate level netlist'. An example of software used to do this might be DesignCompiler, by Synopsis.
Back End Design
- The 'back end' of the design cycle refers to converting your gate level netlist into a 'picture' of an ASIC that would be understood by a silicon foundry.
- First step would be to run initial floorplanning and place and route, which is essentially picking where you want each gate in your design to be positioned in the IC, as well as figuring out how to connect each of these gates in a finite layer of wires.
- At this point you might run timing checks (see: Synopsis PrimeTime) to make sure that your design meets your required clock frequency.
- Once you have your design fully specified, then you need more software (ex. Cadence Virtuoso) which can export your design into the file formats understood by a foundry (GDSII, for example).
Fabrication
- At this point, you have your GDSII in hand, and you call up a contract foundry like TSMC, negotiate with them, and then hand them several million dollars and your GDSII, and wait for 3-6 months. TSMC then takes your design, creates the layer masks, and etches several thousand of your designs into wafers, then slices the wafers up for packaging.
- The ASICs at that point likely go to a contract assembly, where they will be bumped (solder applied to the pads on the bottom of the silicon for soldering to a package), and then packaged (the bumped chip will be attached to whatever kind of package you require, be that QFP, DIP, BGA, or whatever you need).
- At this point your IC is packaged and ready to go, and will be shipped back to you.
There's also a lot of testing that goes on between each step here which I've mostly omitted. Also note that each piece of software mentioned here likely costs in the 6 figure range, and there's probably a few more that I neglected to mention.
Also as I mentioned in my comment, here's an informative excel sheet which gives a rough estimate of the costs of each step: http://www.dz.ee.ethz.ch/?id=1592
Actually the biggest cost is the design itself, then followed by the fab NRE (Fracture costs and mask making).
The biggest risk that you have from a using a Shuttle/MPW is that you often are on the same mask set as someone who is experimenting or who may not understand areal density rules. The worst is when you have some grad student playing around with inductors and ruining the plananarization of adjacent chips. If you are doing something more advanced or needing better matching then you should forget it. Most P&R tools should be OK for routing density, it's the odd wild card that you share the mask with that can screw you up.
Do keep in mind that with an ASIC fabless model, "proof" of a good wafer run is the from the process monitors that the fab measures. NOT your design yielding, that is your responsibility.
The next step up, before a full production mask set is the placement of multiple layers on one mask to reduce the mask making costs. This mask this then used (with blading) and may reduce mask costs to 1/4 or 1/3 (fracture costs stay the same). But the fab will not go to production with this as it slows things down. Not all fabs offer this, and different fabs use different terms for this service.
Best Answer
We used an ASIC in a number of products where a microcontroller used too much power. It was a fairly simple device, a couple of hundreds gates, and had to consume less than 100 nA static, which for microcontrollers at the time was not possible. Price was comparable to a microcontroller due to high quantities; you'll probably need >100 k/yr.
An FPGA would not only have been overkill, costing a lot more, but would have needed an external code Flash, which added to the already bigger footprint.