Electronic – What are the X symbols in a board layout file

Big names in EDA software are Synopsys, Cadence, Mentor, and Magma.

Here is some of the software typically involved in a standard-cell ASIC flow:

HDL simulators read an RTL description of the design (typically written in Verilog or VHDL) and mimic the behavior of the hardware described by the RTL. Wikipedia has a list of Verilog simulators; the list notes which ones also support VHDL.

Synthesis tools read the RTL description and map it onto the cells available in your target library. The cell library is usually described in .db format, and may be provided either by your foundry or by a third-party library provider. The output of the synthesis tool may also be Verilog, but it won't have any high-level constructs, only cell instantiations and wires. This is called a netlist. Wikipedia has a list of tools.

Place and route (P&R) tools take the netlist and search for a physical implementation of that netlist. This involves placing all of the cells in two dimensions and figuring out how to route the connections between the cells. Examples are IC Compiler, Encounter, and Blast Fusion.

As a design goes through P&R there will be additional quality checks including static timing analysis (using e.g. PrimeTime), layout vs. schematic, and DRC.

Create a footprint with GND and AGND pads. Draw copper between these pads. Yes, this will produce a DRC "Overlap" error as shown below:

This is OK. There three buttons at the bottom:

• Clear all
• Processed
• Approve

"Clear all" will temporarily clear the list for this run of the DRC. I'm not sure why that's useful; just close the window if you want it shortened.

"Processed" will fade out the color of the red X. This is potentially useful if you're iterating through a long list of DRC errors and fixing them as you go; you can keep track of the ones you think you've corrected.

"Approve" is the only one I use on a regular basis. This moves the error from the errors list to the approved list:

and keeps it there on subsequent runs of the DRC. Note that this only moves this specific error with this specific pair of nets at this specific location. Closing this window and running the DRC again produces the notification "DRC: 1 approved errors"

and no "DRC Errors" dialog. You can get this dialog back by creating an error, or (preferably) the errors command, the yellow exclamation point in the above screenshot, or the menu Tools -> Errors.

The "Approve" functionality exists for a reason, the same reason that we have tools like

#pragma GCC diagnostic ignored "-Warning"

Sometimes, it's OK to ignore a DRC error. This is one of those times.