Electronic – What are the XGMII control pins

Yes, they are required. Your circuit shows a twisted pair ethernet connection. Each pair must be terminated with its characteristic impedance to maintain signal integrity. The resistors you mention effectively put 100 Ω load on the inboard side of the pulse transformer. In this case, it is a 1:1 transformer, so that is also the load seen on the cable end.

If you leave them off, the voltage levels will be higher than expected, and reflections will occur at the ends of the twisted pair at the transformer. How much this matters depends on the length of the cable and the speed you are running the ethernet at. In any case, leaving off the terminating resistors is a bad idea.

If you don't have 49.9 Ω, use something as close as possible for short term testing with short cables while you're waiting for the right resistors to arrive. I wouldn't ship product with these resistors a few percent off, but for bench testing and debugging other parts of the system, especially if you keep the ethernet cable short, you'll probably get away with it. Either of the common values of 47 Ω or 51 Ω will probably be fine for bench testing under controlled conditions.

That's a doozy of a question. What's the research for?

I know the approach I'm going to suggest won't resolve the problem with the tools complaining, but it might minimize the skew in an actual implementation. I'm not familiar with Altera FPGA's, I've worked mostly with Xilinx S3 and S6 parts; I know this approach can be made to work in an S3, but not an S6, so it might be possible in your case.

In the S3, you can make small adjustments to the phase of the managed clocks (see pg4,5); in a research paper that I've read (I'm still looking for it, will update with a link if/when I find it), the researchers used this capability and a feedback loop to fine-tune the synchronization of a comms link.

If your FPGA has similar capabilities then you might be able to do something similar: use feedback loops to synchronize your three PLL's. It might also be able to help with the problem that three external clock sources and three PLL's will never have identical frequencies. They may be close - to within a few ppm - but never identical.