I am having trouble finding explicit evidence on any FPGA vendors website that their chip supports the verilog-ams and/or verilog-a. Do all these chips support it, or is it only "mixed-signal" chips, or something different entirely.
Electronic – What FPGA chips support verilog-ams or verilog-a
fpgaverilog
Related Solutions
A short answer would be: yes; a longer answer would be: it is not worth your time.
An FPGA itself can run a completely asynchronous design no problem. The result you get is the problem since timing through any FPGA is not very predictable. The bigger problem is the fact that your timing and resultant design will almost definitely vary between different place and route sessions. You can put in constraints on individual asynchronous paths making sure that they do not take too long, but I'm not quite sure that you can specify a minimum delay.
In the end it means that your design will be unpredictable and potentially completely variable with even a slight design change. You'd have to look through the entire timing report every time you change anything at all just to make sure that it would still work. On the other hand, if the design is synchronous, you just look for a pass or fail at the end of place and route (assuming your constraints are setup properly, which doesn't take long at all).
In practice people aim for completely synchronous designs but if you need to simply buffer or invert a signal, you don't need to go through a flip flop as long as you constrain it properly.
Hope this clears it up a bit.
Inouts are actually "wire" so you can't use any procedural/sequential assignments (where the left hand side must be a reg). Generally speaking:
- input : internally must always be of type net, externally the inputs can be connected to a variable of type reg or net.
- output : internally can be of type net or reg, externally the outputs must be connected to a variable of type net.
- inout : internally or externally must always be type net, can only be connected to a variable net type.
A common approach is to have an "enable" signal for the output of your inout, and to drive to high impedance if the output is not enabled. In your case direction is playing that role.
So try this instead:
module test(
input clk, // The standard clock
input direction, // Direction of io, 1 = set output, 0 = read input
input data_in, // Data to send out when direction is 1
output data_out, // Result of input pin when direction is 0
inout io_port // The i/o port to send data through
);
reg a, b;
assign io_port = direction ? a : 1'bz;
assign data_out = b;
always @ (posedge clk)
begin
b <= io_port;
a <= data_in;
end
endmodule
The hardware corresponding to the above code would look something like this:
Best Answer
I know of no significant FPGA manufacturer that supports analog-anything, so I don't see why they would support Verilog-AMS or Verilog-A.
For the record (because someone will try to point this out as a "flaw" in my logic): PLL's, ADC's, DAC's, and high speed transceivers are NOT analog circuits in this context. Although modern FPGA's have these blocks in them, the analog parts are not re-configurable and the analog stuff is not exposed to the Verilog/VHDL programmer.
Every couple of years some new FPGA maker pops up claiming to have "Analog FPGA's" or some similar buzzword. Most of the time it's the same FPGA as before, just bought by a new company. I've looked into it in the past and the analog performance wasn't great (signal to noise, dynamic range, frequency response, etc). Usually these "new" FPGA companies never go into production and soon close their doors. I can't remember what the names of any of these companies are, and a quick Google search shows no manufacturers doing anything in the past year.
The closest to an "Analog FPGA" that I know of today is the Cypress Semiconductor PSoC stuff. Although you have to use their graphical user interface to configure the analog blocks and can't use anything like a "language".