Electronic – What happens when an FPGA is powered on and left unconfigured

fpgapowerprogrammable-logic

I am trying to get a general understanding on what happens if you leave an FPGA unprogrammed for a long duration of time.

Suppose you have an FPGA and you leave it unprogrammed for a long period of time (several minutes to hours after power-on), i.e. no bitstream on it, is this bad for the device? Is it recommended to have some bitstream on a powered-on FPGA at all times? What is the general opinion regarding this?

Are the results different on different devices or manufacturers (Xilinx vs. Altera vs. others)?

Additional Info:

I have a custom SoC board which uses a Xilinx Virtex-6 FPGA. I also have a Xilinx ML605 which I use for reference purposes.

Custom board: I power-on the board. I notice that I get a short duration of time to program it using XMD (Xilinx Microprocessor Debugger). If I lose the 20-30 sec window, I have to switch off and switch on the board before trying again. This does not happen with an ML605.

When I try to program the custom board over XMD, I get something like:

Error: Device Reset by JPROGRAM command, failed. INIT_COMPLETE did not go high.

Let me know what you think.

Best Answer

This is an interesting question. From personal experience, I have left FPGAs powered up for hours in an unprogrammed state while performing checks on the rest of the circuitry when a new board comes in from the assembly house. I have not noticed any detrimental effects from doing so. But I've honestly never thought about it.

I looked around to try and find a recommendation from an FPGA manufacturer but could not find one. The only statement I found regarding this state is from a Lattice whitepaper and regards the design of the FPGA itself and not how it should be used:

Pre-Programmed Static Quiescent Device Power Consumption is the amount of power consumed by the FPGA prior to the device being programmed. For quiescent device power consumption the FPGA is in a non-programmed state, yet has been powered. It is important that the device not consume significant power during this time, as conceptually the FPGA device could draw excessive power and potentially shut down power supplies, preventing the board from successfully initializing itself and the system.
The FPGA supplier therefore has to carefully design transistors that have a low static 3 Designing for Low Power A Lattice Semiconductor White Paper power footprint, without compromising in areas where higher performance is required (e.g. I/O and SERDES)

Xilinx likewise mentions what the quiescent current is so that you can design your power supply accordingly. But does not mention what the effect on the device is of leaving it in such a state:

Static or quiescent power is mainly dominated by transistor leakage current. When this current is listed in data sheets, it is listed as ICCINTQ and is the current drawn through the VCCINT supply powering the FPGA core.

I would be very interested to hear if anyone has experienced damage to a device from leaving it in a quiescent state. But I think as long as the power supply is properly matched to the device, there should be no problem.

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Electronic – Pipelining and clock frequency issue

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.

Electronic – Cheap/old consumer devices to recover FPGA boards from

I'd go for anything Video (especially HD video) related:

these boards often have reasonable FPGAs
tend to be on a reasonable host interface
are usually rather hard to kill due to the studio environments

One of favourite FPGA projects of a friend of mine, http://nsa.unaligned.org/, used HD transform boards.

Another of my personal favourites that I abused a bit myself, is a BlackMagick Intensity HD capture card, coming with a nice set of video peripherals, a decent microcontroler, and an Spartan 3.

After some abuse, it's probably the cheapest non-academic devkit for PCI/PCIe work on FPGA. It seems to be going new for $120-$150 on ebay these days, and you can probably score one with damaged video interface chips.

Best Answer

Related Solutions

Electronic – Pipelining and clock frequency issue

Electronic – Cheap/old consumer devices to recover FPGA boards from

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