AXI4 Protocol – Simultaneous Read and Write to Same Address

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I have a doubt regarding the AXI3/4 protocol. Assume a hypothetical scenario where a single master issues a valid Read and Write transaction to the same address simultaneously.

  1. From the AXI specification, I understand that there is no interdependence between reads and writes and each has a channel of its own. With this in mind, is the above scenario valid?

  2. In case the above scenario is valid, is there a specific order in which these requests are served? (so that there is determinism in the type of response to expect from the master, since there are two ways this could end)

I am aware that (2) can depend on a lot of factors related to the master (posted writes, wait for response read, instruction execution for read after write etc.) and that AXI offers semaphore mechanisms through Exclusive Accesses. But these aside, what should be the expected behaviour?

Best Answer

If the transaction is indicated as "non-modifiable," and both the Read and Write commands use the same ARID/AWID, the order must be preserved. This doesn't cover the case of simultaneous Read and Write commands, which is certainly possible for AXI.

Here's some additional info I found in section A4.3.2 of the AXI Spec (ARM document IHI 0022F.b). My answer is an interpretation of this excerpt:

Ordering between the independent read and write channels can only be guaranteed if a transaction in one direction is issued only after any earlier transaction in the other direction has received a response. If a transaction in one direction is issued before receiving the response to any earlier transaction in the other direction, then no ordering exists between the transactions.

If both transactions arrive at the AXI slave simultaneously, the behavior depends on the slave. For a dual-port RAM, you could conceivably read while writing to the same address. The Read result would then depend on the dual-port RAM controller. For something like DDR3 which can't have simultaneous R/W, the ordering behavior depends on the R/W priority in the controller, again.

Later in section A6.1, this is confirmed even more explicitly:

Read and write address channels are independent and in this specification, are defined to be in different directions. If an ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transaction before issuing the second transaction.

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