I am analysing some verilog code and found something like
wire z = |a & b;
while simultation the code behaves just like
wire z = a & b;
so i was wondering what is the meaning of the |
(pipe) symbol? Does it have any impact on the simulation/synthesis?
Best Answer
This is a bit-wise reduction operator.
|a & b
means you apply a logical OR to all bits ofa
(producing a single bit) and then do a logical AND of that bit andb
.|a
has no effect whena
is a single bit.Nevertheless, it's quite common to see bit-wise reduction applied to single bit values. One typical case is auto-generated code where the actual width of
a
may depend on the configuration. Another possibility is this being legacy code wherea
once had several bits. Whena
became a single bit value, this line was still technically correct so the now unneeded reduction operator was left in.