diagram
I always see such signals (colored in the image) in a timing diagram. Now I've figured out that they're called:
signals.
But why isn't it all drawn as high-active signals (so that the blue area is visualized like the red one)!? What's the reason for that diversity ?
Make your own (readable) style, using well hand draw schematics, and embed some usefull information. Below is one of the best templates that I use.
...if I understand well.
Z means high impedance = "disconnected from the wires" This is the 3rd alternative to 0 and 1 in 3-state outputs. It's used to enable several devices to output their data to the same wires in their turns. 3-state outputs are the basis for the data buses in the computers.Output enable =0 disconnects the device. The red blocks are the 3-state capable buffers. They sometimes have enhanced long line drive capability, Standard logic family members do not have that capability unless otherwise stated in the datasheet.
The dual clock input D-like flip-flops (green) are not full D type flip-flops because they need a clock pulse and the same as inverted. The one inverter delay may have some role in its function. Anyway the resulted function is the same as a chain of D -FFs. The symbol is not standard. It follows manufacturers own conventions.
As commented already, one black connection dot is missing from the clock pulse distribution.
The upper row (blue) is a battery of D latches that keep the data stable when the lower battery is shifting its content to the right.
Latches are not triggered at the edge. Their outputs follow the D-inputs as long as the Strobe=1. The outputs freeze when the Strobe is swicthed to 0.
This IC is used to convert serial data to parellel and also to store one byte that is received one bit at a time from the serial input. Several IC:s can be chained.
This IC is still useful to expad the output capability of a microcontroller. Three of these chained give 24 outputs that need only 3 outputs from microcontroller. In many applications it's not harmful that the outputs can be updated quite sparsely, maybe only once in a millisecond.
Best Answer
The graph directly represents the voltage that you apply to the pin. If it were flipped, it would be confusing because it would no longer be a graph of the voltage on the pin.
If you mean to say "why are some signals active low", that is a more complicated question and has many possible answers.
Sometimes it is more convenient to have a signal as active low, such as a reset signal that will rise as the power supply comes up. This might give you the opportunity to put a resistor and capacitor on the pin making a reset delay circuit.
Other times, it may be an "open collector" type signal that can have many devices tied to it, creating a NOR function, or even just allowing a very simple to implement shared signal.
A third possibility is a combination signal such as a read/write direction pin in a bus, where in one state it is read and the other state it is write. That is often represented as \$R/\overline{W}\$.